Semiconductor device

Abstract

A semiconductor device includes: a micro CMOS region including a micro CMOS and a micro interconnect that is connected to the micro CMOS; and a high breakdown voltage device region including a high breakdown voltage device that has a breakdown voltage higher than that of the micro CMOS, and drain and source interconnects that are connected to the high breakdown voltage device and have a width greater than that of the micro interconnect in a plan view. In the high breakdown voltage device region, an electrically-isolated dummy interconnect is not provided adjacent to at least the drain interconnect and the source interconnect.

1 . A semiconductor device comprising:
 a first region including a first transistor and a first interconnect that is connected to the first transistor; and   a second region including a second transistor in which a thickness of a gate insulating film is greater than that of a gate insulating film in the first transistor and a second interconnect that is connected to the second transistor and has a width greater than that of the first interconnect in a plan view,   wherein an electrically-isolated dummy interconnect is provided in the first region,   wherein the electrically-isolated dummy interconnect is electrically connected to the first transistor.   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein the dummy interconnect is arranged adjacent to the first interconnect in the first region.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein the dummy interconnect is not arranged in the second region.   
     
     
         4 . A semiconductor device comprising:
 a first region including a first transistor and a first interconnect that is connected to the first transistor;   a second region including a second transistor in which a thickness of a gate insulating film is greater than that of a gate insulating film in the first transistor and a second interconnect that is connected to the second transistor and has a width greater than that of the first interconnect in a plan view; and   a dummy interconnect that is electrically isolated from both the first region and the second region,   wherein the dummy interconnect is not arranged within the range of a first distance (d 1 ) from the center of the first interconnect in the first region,   the dummy interconnect is not arranged in the range of a second distance (d 2 ) from the center of the second interconnect in the second region, and   d 2 >d 1  is satisfied,   wherein the electrically-isolated dummy interconnect is electrically connected to the first transistor.   
     
     
         5 . The semiconductor device according to  claim 1 ,
 wherein the second transistor has a drain breakdown voltage higher than that of the first transistor.   
     
     
         6 . The semiconductor device according to  claim 1 ,
 wherein the first transistor is a MOS transistor, and   the second transistor is a double-diffused MOS transistor or a laterally diffused MOS transistor.   
     
     
         7 . The semiconductor device according to  claim 1 ,
 wherein the second transistor has a gate breakdown voltage higher than that of the first transistor.   
     
     
         8 . The semiconductor device according to  claim 1 ,
 wherein a plurality of the first interconnects is provided, and   one dummy interconnect or a plurality of dummy interconnects is arranged between the first interconnects in the first region.   
     
     
         9 . The semiconductor device according to  claim 1 ,
 wherein a plurality of the first interconnects and a plurality of the second interconnects are provided, and   a voltage applied between the second interconnects is higher than that applied between the first interconnects.   
     
     
         10 . The semiconductor device according to  claim 1 ,
 wherein an opening portion is formed in the surface of the second interconnect.   
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein a plurality of the opening portions is formed in the surface of the second interconnect, and   a ladder-shaped pattern is formed in the surface of the second interconnect in a plan view.   
     
     
         12 . The semiconductor device according to  claim 11 ,
 wherein a plurality of the opening portions is formed in the surface of the second interconnect, and   a mesh-shaped pattern is formed in the surface of the second interconnect in a plan view.