Arithmetic unit and arithmetic processing method for operating with higher and lower clock frequencies

Abstract

There is a need for providing a battery-less integrated circuit (IC) card capable of operating in accordance with a contact usage or a non-contact usage, preventing coprocessor throughput from degrading despite a decreased clock frequency for reduced power consumption under non-contact usage, and ensuring high-speed processing under non-contact usage. A dual interface card is a battery-less IC card capable of operating in accordance with a contact usage or a non-contact usage. The dual interface card operates at a high clock under contact usage and at a low clock under non-contact usage. A targeted operation comprises a plurality of different basic operations. The dual interface card comprises a basic arithmetic circuit group. Under the contact usage, the basic arithmetic circuit group performs one basic operation of the targeted operation at one cycle. Under the non-contact usage, the basic arithmetic circuit group sequentially performs at least two basic operations of the targeted operation at one cycle.

What is claimed is: 
     
         1 . An arithmetic processing method for an arithmetic unit that is supplied with a clock and is capable of performing an operation in any of a high clock mode in which a specified clock frequency is supplied and a low clock mode in which a specific clock frequency lower than that of the high clock mode is supplied, the arithmetic unit comprising:
 an execution section and   a clock mode storage section which receives and stores, in accordance with a supplied clock frequency, one of high clock mode information and low clock mode information from an external circuit,   the external circuit outputting the high clock mode information indicative of the high clock mode when a clock frequency in the high clock mode is supplied, and outputting the low clock mode information indicative of the low clock mode when a clock frequency in the low clock mode is supplied,   wherein the execution section performs one of the basic operations in the targeted operation at one cycle of the clock frequency when the clock mode storage section stores the high clock mode information, and   wherein the execution section sequentially performs at least the two basic operations in the targeted operation at one cycle of the clock frequency when the clock mode storage section stores the low clock mode information.