Semiconductor device having metal gate and manufacturing method thereof
Abstract
A semiconductor device having metal gate includes a substrate, a first metal gate positioned on the substrate, and a second metal gate positioned on the substrate. The first metal gate includes a first p-work function metal layer, an n-work function metal layer, and a gap-filling metal layer. The second metal gate includes a second p-work function metal layer, the n-work function metal layer, and the gap-filling metal layer. The first p-work function metal layer and the second p-work function metal layer include a same p-typed metal material. A thickness of the first p-work function metal layer is larger than a thickness of the second p-work function metal layer. The first p-work function metal layer, the second p-work function metal layer, and the n-work function metal layer include a U shape.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device having metal gate comprising:
a substrate; a first metal gate positioned on the substrate, the first metal gate comprising a first p-work function metal layer, an n-work function metal layer, and a gap-filling metal layer; and a second metal gate positioned on the substrate, the second metal gate comprising a second p-work function metal layer, the n-work function metal layer, and the gap-filling metal layer, wherein the first p-work function metal layer and the second p-work function metal layer comprise a same p-typed metal material, a thickness of the first p-work function metal layer is larger than a thickness of the second p-work function metal layer, and the first p-work function metal layer, the second p-work function metal layer and the n-work function metal layer comprise a U shape.
2 . The semiconductor device having metal gate according to claim 1 , further comprising a high-k gate dielectric layer formed in between the first metal gate and the substrate, and between the second metal gate and the substrate.
3 . The semiconductor device having metal gate according to claim 2 , wherein the high-k gate dielectric layer comprises a U shape.
4 . The semiconductor device having metal gate according to claim 2 , wherein the high-k gate dielectric layer comprises a flat shape.
5 . The semiconductor device having metal gate according to claim 2 , further comprises an interfacial layer positioned between the high-k gate dielectric layer and the substrate.Join the waitlist — get patent alerts
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