Multi-height multi-composition semiconductor fins

Abstract

A dielectric material layer is formed on a semiconductor-on-insulator (SOI) substrate including a top semiconductor layer containing a first semiconductor material. An opening is formed within the dielectric material layer, and a trench is formed in the top semiconductor layer within the area of the opening by an etch. A second semiconductor material is deposited to a height above the top surface of the top semiconductor layer employing a selective epitaxy process. Another dielectric material layer can be deposited, and another trench can be formed in the top semiconductor layer. Another semiconductor material can be deposited to a different height employing another selective epitaxy process. The various semiconductor material portions can be patterned to form semiconductor fins having different heights and/or different compositions.

1 .- 15 . (canceled) 
     
     
         16 . A semiconductor structure comprising:
 an insulator layer;   a first-type semiconductor fin comprising a first single crystalline semiconductor material and located on a planar top surface of said insulator layer;   a second-type semiconductor fin comprising a vertical stack of a portion of said first single crystalline semiconductor material and a portion of a second single crystalline semiconductor material that is different from said first single crystalline semiconductor material; and   a third-type semiconductor fin comprising a vertical stack of another portion of said first single crystalline semiconductor material and a portion of a third single-crystalline semiconductor material that is different from said first single crystalline semiconductor material.   
     
     
         17 . The semiconductor structure of  claim 16 , wherein all portions of said first single crystalline semiconductor material among said first-type, second-type, and third-type semiconductor fins contact said insulator layer, have an identical crystallographic structure, and have an identical spatial orientation for each crystallographic axis of said identical crystallographic structure. 
     
     
         18 . The semiconductor structure of  claim 16 , wherein each of said first-type semiconductor fin, said second-type semiconductor fin, and said third-type semiconductor fin have different heights. 
     
     
         19 . The semiconductor structure of  claim 16 , wherein said first single crystalline semiconductor material is single crystalline silicon, said second single crystalline semiconductor material is a first single crystalline silicon-containing alloy, and said third single crystalline semiconductor material is a second single crystalline silicon-containing alloy having a different composition from said first single crystalline silicon-containing alloy. 
     
     
         20 . The semiconductor structure of  claim 19 , wherein each of said first single crystalline silicon-containing alloy and said second single crystalline silicon-containing alloy is selected from a single crystalline silicon-germanium alloy, a single crystalline silicon-carbon alloy, and a single crystalline silicon-germanium-carbon alloy. 
     
     
         21 . The semiconductor structure of  claim 16 , wherein said second-type semiconductor fin is located on a second portion of said planar top surface of said insulator layer, and said third-type semiconductor fin is located on a third portion of said planar top surface of said insulator layer. 
     
     
         22 . The semiconductor structure of  claim 16 , wherein said insulator layer is a contiguous layer present beneath each of said first-type semiconductor fin, said second-type semiconductor fin and said third-type semiconductor fin. 
     
     
         23 . The semiconductor structure of  claim 22 , wherein a handle substrate is located beneath said insulator layer. 
     
     
         24 . The semiconductor structure of  claim 16 , wherein a first gate structure straddles over a portion of said first-type semiconductor fin, a second gate structure straddles over a portion of said second-type semiconductor fin, and a third gate structure straddles over a portion of said third-type semiconductor fin. 
     
     
         25 . The semiconductor structure of  claim 24 , wherein said first gate structure, said second gate structure and said third gate structure have a same height. 
     
     
         26 . The semiconductor structure of  claim 24 , further comprising a dielectric spacer located on sidewall surfaces of said first gate structure, said second gate structure and said third gate structure. 
     
     
         27 . The semiconductor structure of  claim 26 , wherein said dielectric spacer has a height that is less than a height of each of said first gate structure, said second gate structure and said third gate structure. 
     
     
         28 . The semiconductor structure of  claim 16 , wherein said portion of said first single crystalline semiconductor material has sidewall surfaces that are vertically coincident with sidewall surfaces of said portion of said second single crystalline semiconductor material. 
     
     
         29 . The semiconductor structure of  claim 28 , wherein said another portion of said first single crystalline semiconductor material has sidewall surfaces that are vertically coincident with sidewall surfaces of said portion of said third single-crystalline semiconductor material.