Thyristor random access memory

Abstract

Devices and methods for forming a device are presented. The device includes a substrate having a well of a first polarity type and a thyristor-based memory cell. The thyristor-based memory cell includes at least a first region of a second polarity type adjacent to the well, a gate which serves as a second word line disposed on the substrate, at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate, and at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate. At least the heavily doped first layer of the second polarity type is self-aligned with side of the gate.

What is claimed is: 
     
         1 . A device comprising:
 a substrate having a well of a first polarity type; and   a thyristor-based memory cell comprising
 at least a first region of a second polarity type adjacent to the well, 
 a gate which serves as a second word line disposed on the substrate, 
 at least a first layer of the first polarity type disposed adjacent to the first region of the second polarity type and adjacent to the gate; and 
 at least a heavily doped first layer of the second polarity type disposed on the first layer of the first polarity type and adjacent to the gate, wherein at least the heavily doped first layer of the second polarity type is self-aligned with side of the gate. 
   
     
     
         2 . A method of forming a device comprising:
 providing a substrate having a well of a first polarity type;   forming a thyristor-based memory cell comprising
 forming at least a first region of a second polarity type adjacent to the well, 
 forming a gate on the substrate, wherein the gate serves as a second word line, 
 forming at least a first layer of the first polarity type adjacent to the first region of the second polarity type and adjacent to the gate, and 
 forming at least a heavily doped first layer of the second polarity type on the first layer of the first polarity type and adjacent to the gate, wherein at least the heavily doped first layer of the second polarity type is self-aligned with side of the gate. 
   
     
     
         3 . The method of  claim 2  wherein the thyristor-based memory cell comprises a 2-bits-per-cell structure and wherein:
 forming the gate comprises forming a dummy gate; 
 forming the at least a first region of the second polarity type adjacent to the well comprises forming first and second regions of the second polarity type in the well adjacent to first and second sides of the dummy gate; 
 forming the at least a first layer of the first polarity type comprises forming first and second elevated layers of the first polarity type over the first and second regions of the second polarity type adjacent to the first and second sides of the dummy gate; and 
 forming at least a heavily doped first layer of the second polarity type comprises forming heavily doped first and second layers of the second polarity type on the first and second elevated layers of the first polarity type. 
 
     
     
         4 . The method of  claim 3  wherein the first and second regions of the second polarity type in the well are formed by implanting second polarity type dopants into the well and wherein the implant is self-aligned with respect to the dummy gate. 
     
     
         5 . The method of  claim 3  wherein the first and second regions of the second polarity type comprise band-engineered regions. 
     
     
         6 . The method of  claim 5  wherein the first and second regions of the second polarity type, the first and second elevated layers of the first polarity type, and the heavily doped first and second layers of the second polarity type are formed by selective epitaxial growth (SEG) process. 
     
     
         7 . The method of  claim 3  wherein:
 the first and second regions of the second polarity type serve as base while the well serves as emitter of cathode portion of the respective bit and the well also serves as a first word line; 
 the first and second elevated layers of the first polarity type serve as base while the heavily doped first and second layers of the second polarity type serve as emitter of anode portion of the respective bit; and 
 the heavily doped first layer of the second polarity type is coupled to a first bit line while the heavily doped second layer of the second polarity type is coupled to a second bit line. 
 
     
     
         8 . The method of  claim 3  comprising:
 removing the dummy gate after forming the heavily doped first and second layers of the second polarity type; 
 forming a trench which extends to within a portion of the well and portions of the first and second regions of the second polarity type; and 
 forming a high-k metal gate structure within the trench, wherein a portion of the high-k metal gate structure extends vertically with respect to a horizontal plane toward the well to be parallel with the first and second regions of the second polarity type with respect to the horizontal plane. 
 
     
     
         9 . The method of  2  wherein the thyristor-based memory cell comprises a 1-bit-per-cell structure and wherein:
 the substrate comprises an isolation region; 
 forming the at least a first region of the second polarity type adjacent to the well comprises forming the first region of the second polarity type in the well and extends to an edge of the isolation region; 
 forming the gate comprises forming a dummy gate, wherein the dummy gate partially overlaps the isolation region; 
 the first layer of the first polarity type is formed on the first region of the second polarity type; and 
 the first layer of the first polarity type and the heavily doped first layer of the second polarity type are formed adjacent to a first side of the dummy gate. 
 
     
     
         10 . The method of  claim 9  wherein:
 the first region of the second polarity type serves as a base while the well serves as an emitter of a cathode portion of the bit and the well also serves as a first word line; 
 the first layer of the first polarity type serves as a base while the heavily doped first layer of the second polarity type serves as an emitter of an anode portion of the bit; and 
 the heavily doped first layer of the second polarity type is coupled to a bit line. 
 
     
     
         11 . The method of  2  wherein the thyristor-based memory cell comprises a 1-bit-per-cell structure and wherein:
 the substrate comprises an isolation region; 
 forming the at least a first region of the second polarity type adjacent to the well comprises forming the first region of the second polarity type over the substrate by SEG process; 
 forming the gate comprises forming a dummy gate, wherein the dummy gate is formed over the first region of the second polarity type; 
 the first layer of the first polarity type is formed on the first region of the second polarity type; and 
 the first layer of the first polarity type and the heavily doped first layer of the second polarity type are formed adjacent to a first side of the dummy gate. 
 
     
     
         12 . The method of  claim 11  comprising forming first and second spacers adjacent to first and second sides of the dummy gate, wherein the first spacer extends to a top surface of the first region of the second polarity type while the second spacer extends to a top of the isolation region. 
     
     
         13 . The method of  claim 12  comprising:
 removing the dummy gate after forming the heavily doped first layer of the second polarity type; 
 forming a trench which extends to within a portion of the first region of the second polarity type; and 
 forming a high-k metal gate structure within the trench, wherein a portion of the high-k metal gate structure extends vertically with respect to a horizontal plane toward the well to be parallel with the first region of the second polarity type with respect to the horizontal plane. 
 
     
     
         14 . The method of  claim 2  wherein the thyristor-based memory cell comprises a 2-bits-per-cell structure and wherein forming the at least a first region of the second polarity type adjacent to the well comprises:
 processing the substrate to form at least first and second fin structures; 
 forming an isolation region between the fin structures; and 
 implanting second polarity type dopants into the first and second fin structures to form first and second regions of the second polarity type. 
 
     
     
         15 . The method of  claim 14  wherein:
 forming the gate comprises forming a dummy gate; 
 forming the at least a first layer of the first polarity type comprises forming first and second elevated layers of the first polarity type over the first and second regions of the second polarity type adjacent to the first and second sides of the dummy gate; and 
 forming at least a heavily doped first layer of the second polarity type comprises forming heavily doped first and second layers of the second polarity type on the first and second elevated layers of the first polarity type. 
 
     
     
         16 . The method of  2  wherein the thyristor-based memory cell comprises a 1-bit-per-cell structure and wherein:
 the substrate comprises an isolation region; 
 forming the at least a first region of the second polarity type adjacent to the well comprises
 processing the substrate to form at least a first fin structure; and 
 implanting second polarity type dopants into the first fin structure to form the first region of the second polarity type. 
 
 
     
     
         17 . The method of  claim 16  wherein:
 forming the gate comprises forming a dummy gate, wherein the dummy gate at least partially overlaps the isolation region and the first region of the second polarity type; 
 the first layer of the first polarity type is formed on the first region of the second polarity type; and 
 the first layer of the first polarity type and the heavily doped first layer of the second polarity type are formed adjacent to a first side of the dummy gate. 
 
     
     
         18 . The method of  claim 2  wherein the thyristor-based memory cell comprises a 1-bit-per-cell structure and wherein:
 forming the gate comprises forming a dummy gate; and 
 forming the at least a first layer of the first polarity type comprises forming first lightly doped and second heavily doped regions of the first polarity type in the well adjacent to first and second sides of the dummy gate. 
 
     
     
         19 . The method of  claim 18  wherein:
 the first region of the second polarity type serves as a base while the second heavily doped region of the first polarity type serves as an emitter of a cathode portion of the bit; 
 the first lightly doped region of the first polarity type serves as a base while the heavily doped first layer of the second polarity type serves as an emitter of an anode portion of the bit; and 
 the heavily doped first layer of the second polarity type is coupled to a bit line while the second heavily doped region of the first polarity type is coupled to a first word line. 
 
     
     
         20 . The method of  claim 18  comprising:
 removing the dummy gate after forming the heavily doped first layer of the second polarity type; 
 forming a trench which extends to within a portion of the first region of the second polarity type; 
 forming a BE region within the trench, wherein a top surface of the BE region is substantially coplanar with top surfaces of the regions of the first polarity type; and 
 forming a high-k metal gate structure within the trench over the BE region. 
 
     
     
         21 . The method of  claim 2  wherein the thyristor-based memory cell comprises a 1-bit-per-cell structure and wherein:
 forming the gate comprises forming a dummy gate; 
 forming the at least a first layer of the first polarity type comprises forming first elevated layer of the first polarity type over the first region of the second polarity type adjacent to a first side of the dummy gate; and comprising 
 forming a heavily doped region of the first polarity type in the first region of the second polarity type adjacent to second side of the dummy gate. 
 
     
     
         22 . The method of  claim 21  comprising:
 removing the dummy gate after forming the heavily doped first layer of the second polarity type; 
 forming a trench which extends to within a portion of the first region of the second polarity type; 
 forming a BE region within the trench, wherein a top surface of the BE region is substantially coplanar with a top surface of the heavily doped region of the first polarity type; and 
 forming a high-k metal gate structure within the trench over the BE region.