Field effect transistor structure having one or more fins

Abstract

A field effect transistor (FET) having one or more fins provides an extended current path as compared to conventional finFETs. A raised source terminal is disposed on a fin adjacent to a sidewall spacer of a gate structure. The drain terminal and a first portion of the gate structure overlie a first well of a first conductivity type. A raised drain terminal is disposed such that it is spaced apart from the gate structure sidewalls. In some embodiments the drain terminal is disposed on a second, separate fin. The drain terminal and a second portion of the gate structure overlie a second well of a second conductivity type.

What is claimed is: 
     
         1 . A transistor, comprising:
 a first fin disposed on a first region of a substrate, the first fin having a first end and second end;   a second fin disposed on a second region of the substrate and spaced apart from the first fin, the second fin having a first end and a second end;   a gate structure disposed on the first fin, the gate structure having a first sidewall and a second sidewall, with the second sidewall vertically aligned with the second end of the first fin;   a first source/drain (S/D) terminal disposed on the first fin, adjacent to the first sidewall of the gate structure;   a second S/D terminal disposed on the second fin;   a first fin termination structure disposed on the first fin and vertically aligned to the first end of the first fin;   a second fin termination structure disposed on the second fin and vertically aligned to the second end of the first fin; and   a third fin termination structure disposed on the second fin and aligned to the second end of the second fin.   
     
     
         2 . The transistor of  claim 1 , wherein the second S/D terminal is disposed between on the second fin between the second fin termination structure and the third fin termination structure. 
     
     
         3 . The transistor of  claim 1 , wherein the second end of the first fin faces, and is spaced apart from the first end of the second fin. 
     
     
         4 . The transistor of  claim 1 , further comprising a shallow trench isolation structure disposed in a recess in the surface of the substrate between the second end of the first fin and the first end of the second fin. 
     
     
         5 . The transistor of  claim 1 , wherein the first region of the substrate includes a first sub-region doped with a first concentration of dopant atoms of a first conductivity type, a second sub-region doped with a second concentration of dopant atoms of a second conductivity type, and the second region of the substrate includes a third sub-region doped with the second concentration of dopant atoms of the second conductivity type; 
     
     
         6 . The transistor of  claim 1 , wherein the first conductivity type is p-type and the second conductivity type is n-type. 
     
     
         7 . The transistor of  claim 1 , wherein the first concentration of dopants is between 1×10 17 /cm 3  and 5×10 18 /cm 3 . 
     
     
         8 . The transistor of  claim 1 , wherein the second concentration of dopants is between 1×10 17 /cm 3  and 5×10 18 /cm 3 . 
     
     
         9 . The transistor of  claim 1 , wherein the first S/D terminal comprises epitaxial silicon and the second S/D terminal comprises epitaxial silicon. 
     
     
         10 . The transistor of  claim 1 , further comprising a first sidewall spacer disposed along the second sidewall of the gate structure and along the second end of the first fin.