Finfet fabrication method

Abstract

Embodiments of the present invention provide an improved method for fabrication of fin field effect transistors (finFETs). Sacrificial regions are formed on a semiconductor substrate. Spacers are formed adjacent to two sides of the sacrificial regions. Fins are formed based on the spacers. One set of spacers is treated as dummy spacers, and is removed prior to fin formation, leaving the other set of spacers to be used for forming fins on the final semiconductor structure. All the fins on the final semiconductor structure are formed from spacers on one side of the sacrificial material. This reduces variation in width of the fins.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor substrate comprising a substrate material; and   a plurality of fins, wherein each fin comprises a lower region comprising the substrate material, a middle region comprising a nitride material, and an upper region comprising a spacer material, and the fins have substantially equal widths.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the spacer material comprises silicon nitride. 
     
     
         3 . The semiconductor device of  claim 1 , further comprising:
 a plurality of shallow trench isolation (STI) regions in the semiconductor substrate, wherein each STI region is disposed between adjacent fins.   
     
     
         4 . The semiconductor device of  claim 3 , wherein the plurality of STI regions comprise silicon oxide. 
     
     
         5 . The semiconductor device of  claim 3 , wherein the distance between each STI region and a first adjacent fin ranges from about 15 nanometers to about 30 nanometers. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the middle region has a height ranging from about 10 nanometers to about 100 nanometers. 
     
     
         7 . A semiconductor device, comprising:
 a semiconductor substrate comprising a substrate material; and   a plurality of finFET devices, wherein each finFET device comprises a single fin, wherein the fin of each of the plurality of FinFET devices comprises a lower region comprising the substrate material, a middle region comprising a nitride material, and an upper region comprising a spacer material, and wherein the fins of the plurality of FinFET devices are formed by a process comprising:   forming a nitride liner on the semiconductor substrate;   forming a plurality of sacrificial material regions on the nitride liner;   forming a first set of spacers on a first side of each of the sacrificial material regions and a second set of spacers on a second side of each of the sacrificial material regions;   removing the plurality of sacrificial material regions;   removing each of the second set of spacers while preserving the first set of spacers.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the spacer material comprises silicon nitride. 
     
     
         9 . The semiconductor device of  claim 7 , further comprising:
 a plurality of shallow trench isolation (STI) regions in the semiconductor substrate, wherein each STI region is disposed between adjacent fins.   
     
     
         10 . The semiconductor device of  claim 9 , wherein the plurality of STI regions comprise silicon oxide. 
     
     
         11 . The semiconductor device of  claim 9 , wherein the distance between each STI region and a first adjacent fin ranges from about 15 nanometers to about 30 nanometers. 
     
     
         12 . The semiconductor device of  claim 7 , wherein the middle region has a height ranging from about 10 nanometers to about 100 nanometers. 
     
     
         13 . A semiconductor device, comprising:
 a semiconductor substrate comprising a substrate material; and   a plurality of fins, wherein each fin comprises a lower region comprising the substrate material, a middle region comprising a nitride material, an upper region comprising a spacer material, and a first side, wherein a pitch between the first sides of adjacent fins ranges from about 50 nanometers to about 90 nanometers.   
     
     
         14 . The semiconductor device of  claim 13 , wherein the spacer material comprises silicon nitride. 
     
     
         15 . The semiconductor device of  claim 13 , further comprising:
 a plurality of shallow trench isolation (STI) regions in the semiconductor substrate, wherein each STI region is disposed between adjacent fins.   
     
     
         16 . The semiconductor device of  claim 15 , wherein the plurality of STI regions comprise silicon oxide. 
     
     
         17 . The semiconductor device of  claim 15 , wherein the distance between each STI region and a first adjacent fin ranges from about 15 nanometers to about 30 nanometers. 
     
     
         18 . The semiconductor device of  claim 13 , wherein the middle region has a height ranging from about 10 nanometers to about 100 nanometers.