Method of forming a thin substrate chip scale package device and structure

Abstract

In one embodiment, a method for forming an electronic package structure includes providing a single unit leadframe having first terminals on a first or top surface. An electronic device is attached to the single unit leadframe and electrically connected to the first terminals. The leadframe, first terminals, and the electronic device are encapsulated with an encapsulating material. Second terminals are then formed by removing portions of a second or bottom surface of the leadframe. In one embodiment, the method can be used to fabricate a thin substrate chip scale package (“tsCSP”) type structure.

What is claimed is: 
     
         1 - 20 . (canceled) 
     
     
         21 . A method for forming an electronic package structure comprising:
 providing a single unit leadframe having a first surface with first terminals protruding in a first predetermined array, wherein the first terminals are separated by a plurality of grooves, and wherein the single unit leadframe has a second surface opposite to the first surface, and wherein the second surface is a substantially planar surface;   electrically connecting an electronic chip to the first terminals;   forming an encapsulating layer on the first surface to encapsulate the electronic chip and at least some of the plurality of grooves; and   thereafter selectively removing portions of the second surface of the single unit to form second terminals in a second predetermined array and coupled to the first terminals, wherein the first predetermined array is different than the second predetermined array.   
     
     
         22 . The method of  claim 21 , wherein electrically connecting the electronic chip comprises attaching the electronic chip to the first terminals using conductive solder balls. 
     
     
         23 . The method of  claim 21 , wherein attaching the electronic chip comprises:
 placing an adhesive within a first groove, wherein the adhesive is absent from a second groove;   attaching the electronic chip to one or more of the first terminals using the adhesive, wherein the electronic chip overlaps the first groove; and   attaching conductive structures to bond pads on the electronic chip and to other first terminals, and wherein forming the encapsulating layer includes forming the encapsulating layer in the second groove but not the first groove.   
     
     
         24 . The method of  claim 23 , wherein attaching the conductive structures includes attaching conductive wires. 
     
     
         25 . The method of  claim 21 , wherein forming the encapsulating layer includes forming the encapsulating layer to completely cover side surfaces of the first terminals. 
     
     
         26 . The method of  claim 21 , wherein electrically connecting the electronic chip comprises electrically connecting a semiconductor chip. 
     
     
         27 . The method of  claim 21 , wherein selectively removing portions of the second surface comprises:
 forming a photoresist layer on the second surface;   patterning the photoresist layer to expose portions of the second surface; and   etching the exposed portions of the second surface to form a non-planar second surface.   
     
     
         28 . The method of  claim 21  further comprising forming an insulating layer in spaces between the second terminals. 
     
     
         29 . The method of  claim 21 , wherein providing the single unit leadframe comprises:
 forming a patterned mask on the first surface of the single unit leadframe but not the second surface; and   removing exposed portions of first surface to form the first terminals without forming patterned features in the second surface.   
     
     
         30 . The method of  claim 21 , wherein providing the single unit leadframe comprises providing the second surface absent any patterned features extending inward from the second surface at least where the second surface and the first terminals overlap. 
     
     
         31 . The method of  claim 21 , wherein providing the single unit leadframe comprises providing a second surface that is non-selectively etched. 
     
     
         32 . A method of forming a semiconductor package structure comprising:
 providing a single unit leadframe having a first surface defining first terminals in a first predetermined array, wherein the first terminals are separated by a plurality of gaps, and wherein the single unit leadframe has a second surface opposite to the first surface that is substantially planar;   electrically connecting a semiconductor chip to the first terminals;   forming an encapsulating layer that encapsulates the semiconductor chip, the first terminals, at least some of the plurality of gaps, and at least a portion of the first surface; and   thereafter selectively removing portions of the second surface of the single unit leadframe to form second terminals in a second predetermined array, wherein the first predetermined array has a different pattern than the second predetermined array.   
     
     
         33 . The method of  claim 32 , wherein providing the single unit leadframe comprises providing the second surface free from any patterned features at least where the second surface and the first terminals overlap. 
     
     
         34 . The method of  claim 32 , providing the single unit leadframe comprises:
 forming a patterned mask on the first surface of the single unit leadframe but not the second surface; and   removing exposed portions of first surface to form the first terminals without forming patterned features in the second surface.   
     
     
         35 . The method of  claim 32 , wherein electrically connecting the semiconductor chip comprises:
 placing an adhesive within a first gap, wherein the adhesive is absent from a second gap;   attaching the semiconductor chip to one or more of the first terminals using the adhesive, wherein the semiconductor chip overlaps the first gap; and   attaching conductive structures to bond pads on the semiconductor chip and to other first terminals, and wherein forming the encapsulating layer includes forming the encapsulating layer in the second gap but not the first gap.   
     
     
         36 . The method of  claim 32 , wherein electrically connecting the semiconductor chip comprises electrically connecting both opposing major surfaces of the semiconductor chip to the first terminals. 
     
     
         37 . The method of  claim 32 , wherein electrically connecting the semiconductor chip includes directly attaching bond pads on the semiconductor chip to the first terminals with solder structures in a flip-chip configuration. 
     
     
         38 . The method of  claim 32 , wherein providing the single unit leadframe comprises providing a second surface that is non-selectively etched. 
     
     
         39 . The method of  claim 32  further comprising forming an insulating layer in spaces between the second terminals. 
     
     
         40 . A method for forming a thin substrate chip scale packaged electronic device comprising:
 providing a leadframe comprising a conductive material and having a plurality of first terminal portions protruding from a first surface in a first predetermined pattern, the first predetermined pattern including a plurality of grooves between the first terminal portions, the leadframe further comprising a generally planar second surface that is non-etched in selective manner, wherein the generally planar second surface is opposite to the first surface;   electrically coupling an electronic device to the plurality of first terminal portions;   forming a mold layer covering the electronic device and the plurality of grooves; and   thereafter selectively etching the second surface in a second predetermined pattern to expose portions of the molded encapsulating layer and to provide a plurality of second terminal portions connected to the plurality of first terminal portions with spaces between the plurality of second terminal portions, wherein the second predetermined pattern is different than the first predetermined pattern; and   providing an insulating layer within the spaces, wherein the insulating layer adjoins the molded encapsulating layer.