Semiconductor Package with Multiple Dies

Abstract

A semiconductor package that includes a substrate having a metallic back plate, an insulation body and a plurality of conductive pads on the insulation body, and a semiconductor die coupled to said conductive pads, the conductive pads including regions readied for direct connection to pads external to the package using a conductive adhesive.

1 - 12 . (canceled) 
     
     
         13 - 27 . (canceled) 
     
     
         28 . A semiconductor package comprising:
 a first semiconductor die that includes a first electrode on a surface thereof;   a second semiconductor die that includes a first electrode on a surface thereof;   a support plate, and an insulation body disposed on a first surface of said support plate;   a plurality of laterally spaced conductive pads on said insulation body;   a first one of said conductive pads including a first region coupled to said first electrode of said first semiconductor die with a conductive adhesive body interposed between said first electrode and said first region;   a second one of said conductive pads including a first region coupled to said first electrode of said second semiconductor die with a conductive adhesive body interposed between said first electrode and said first region.   
     
     
         29 . The semiconductor package of  claim 28 , wherein said first one of said conductive pads includes a second region readied for connection to a conductive pad external to said package. 
     
     
         30 . The semiconductor package of  claim 28 , wherein said second one of said conductive pads includes a second region readied for connection to a conductive pad external to said package. 
     
     
         31 . The semiconductor package of  claim 28 , wherein said first semiconductor die includes a second electrode lateral to said first electrode, said second electrode being coupled to a first region of a respective conductive pad with a conductive adhesive body interposed between said second electrode and said first region of said respective conductive pad. 
     
     
         32 . The semiconductor package of  claim 28 , wherein said second semiconductor die includes a second electrode lateral to said first electrode, said second electrode being coupled to a first region of a respective conductive pad with a conductive adhesive body interposed between said second electrode and said first region of said respective conductive pad. 
     
     
         33 . The semiconductor package of  claim 28 , wherein each said first and second semiconductor die includes a third electrode. 
     
     
         34 . The semiconductor package of  claim 33 , wherein each said third electrode is readied for connection using a conductive adhesive body to a conductive pad external to said package. 
     
     
         35 . The semiconductor package of  claim 28 , further comprising another insulation body between said insulation body and said support plate. 
     
     
         36 . The semiconductor package of  claim 35 , further comprising metallic input/output tracks on said another insulation body, and an IC die to operate said first semiconductor die coupled to said metallic input/output tracks. 
     
     
         37 . The semiconductor package of  claim 36 , wherein at least one of said metallic input/output tracks is coupled to a respective second electrode, and at least one of said metallic input/output tracks is coupled to a respective pad having a region readied for connection to a pad external to said package using a conductive adhesive body. 
     
     
         38 . The semiconductor package of  claim 28 , wherein said support plate is metallic. 
     
     
         39 . A semiconductor package comprising:
 a first semiconductor die having a first electrode;   a second semiconductor die having a first electrode;   a support plate and an insulation body disposed on said support plate;   a first conductive pad including a first region coupled to said first electrode of said first semiconductor die with a first conductive adhesive body interposed between said first electrode of said first semiconductor die and said first region.   
     
     
         40 . The semiconductor package of  claim 39  further comprising a second conductive pad including a first region coupled to said first electrode of said second semiconductor die with a first conductive adhesive body interposed between said first electrode of said second semiconductor die and said first region. 
     
     
         41 . The semiconductor package of  claim 39 , wherein each said first and second semiconductor die includes a second electrode lateral to said first electrode. 
     
     
         42 . The semiconductor package of  claim 41 , wherein each said first and second semiconductor die includes a third electrode. 
     
     
         43 . The semiconductor package of  claim 42 , wherein each said third electrode is readied for connection using a conductive adhesive body to a conductive pad external to said package. 
     
     
         44 . The semiconductor package of  claim 39 , wherein said support plate is metallic. 
     
     
         45 . The semiconductor package of  claim 39  further comprising another insulation body between said insulation body and said support plate, a plurality of metallic input/output tracks on said another insulation body, and an IC die to operate said first semiconductor die coupled to said metallic input/output tracks. 
     
     
         46 . The semiconductor package of  claim 40  further comprising another insulation body between said insulation body and said support plate, a plurality of metallic input/output tracks on said another insulation body, and an IC die to operate said second semiconductor die coupled to said metallic input/output tracks. 
     
     
         47 . The semiconductor package of  claim 40  further comprising another insulation body between said insulation body and said support plate, a plurality of metallic input/output tracks on said another insulation body, and an IC die to operate said first and second semiconductor dies coupled to said metallic input/output tracks.