Discrete Three-Dimensional Memory Comprising Off-Die Address/Data Translator

Abstract

The present invention discloses a discrete three-dimensional memory (3D-M). Its 3D-M arrays are located on at least one 3D-array die, while its address/data translator (A/D-translator) is located on a separate peripheral-circuit die. The A/D-translator converts at least an address and/or data between logical space and physical spaces for the 3D-array die. A single A/D-translator die can support multiple 3D-array dies.

What is claimed is: 
     
         1 . A discrete three-dimensional memory (3D-M), comprising:
 a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory cells;   a peripheral-circuit die comprising at least a portion of an address/data translator for converting at least an address and/or data between logical and physical spaces for said 3D-array die, wherein said portion of said address/data translator is absent from said 3D-array die;   wherein said peripheral-circuit die comprises fewer back-end layers than said 3D-array die; and, said 3D-array die and said peripheral-circuit die are separate dice.   
     
     
         2 . The memory according to  claim 1 , wherein said peripheral-circuit die comprises more substrate interconnect layers than said 3D-array die. 
     
     
         3 . The memory according to  claim 1 , wherein said peripheral-circuit die comprises different interconnect materials than said 3D-array die. 
     
     
         4 . The memory according to  claim 1 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM). 
     
     
         5 . The memory according to  claim 1 , wherein said 3D-M comprises a three-dimensional mask-programmed read-only memory (3D-MPROM) or a three-dimensional electrically-programmable read-only memory (3D-EPROM). 
     
     
         6 . The memory according to  claim 1 , wherein said address/data translator is an address translator comprising at least one of an address mapping table, a faulty block table and a wear management table. 
     
     
         7 . The memory according to  claim 1 , wherein said address/data translator is a data translator comprising at least one of an ECC-encoder and an ECC-decoder. 
     
     
         8 . The memory according to  claim 1 , where said 3D-array die comprises a first serializer-deserializer and said peripheral-circuit die comprises a second serializer-deserializer. 
     
     
         9 . The memory according to  claim 1 , further comprising another 3D-array die, wherein said peripheral-circuit die further comprises at least another portion of another address/data translator for said another 3D-array die, and said another portion of said another address/data translator is absent from said another 3D-array die. 
     
     
         10 . The memory according to  claim 1 , wherein said 3D-array and peripheral-circuit dice are located in a memory package, a memory module, a memory card or a solid-state drive. 
     
     
         11 . A discrete three-dimensional memory (3D-M), comprising:
 a 3D-array die comprising at least a 3D-M array including a plurality of vertically stacked memory cells;   a peripheral-circuit die comprising at least a portion of an address/data translator for converting at least an address and/or data between logical and physical spaces for said 3D-array die, wherein said portion of said address/data translator is absent from said 3D-array die;   wherein said peripheral-circuit die comprises different interconnect materials than said 3D-array die; and, said 3D-array die and said peripheral-circuit die are separate dice.   
     
     
         12 . The memory according to  claim 11 , wherein said 3D-array die comprises high-temperature interconnect materials. 
     
     
         13 . The memory according to  claim 11 , wherein said peripheral-circuit die comprises high-speed interconnect materials. 
     
     
         14 . The memory according to  claim 11 , wherein said peripheral-circuit die comprises fewer back-end layers than said 3D-array die. 
     
     
         15 . The memory according to  claim 11 , wherein said peripheral-circuit die comprises more substrate interconnect layers than said 3D-array die. 
     
     
         16 . The memory according to  claim 11 , wherein said 3D-M comprises a three-dimensional read-only memory (3D-ROM) or a three-dimensional random-access memory (3D-RAM). 
     
     
         17 . The memory according to  claim 11 , wherein said address/data translator is an address translator comprising at least one of an address mapping table, a faulty block table and a wear management table. 
     
     
         18 . The memory according to  claim 11 , wherein said address/data translator is a data translator comprising at least one of an ECC-encoder and an ECC-decoder. 
     
     
         19 . The memory according to  claim 11 , further comprising another 3D-array die, wherein said peripheral-circuit die further comprises at least another portion of another address/data translator for said another 3D-array die, and said another portion of said another address/data translator is absent from said another 3D-array die. 
     
     
         20 . The memory according to  claim 11 , wherein said 3D-array and peripheral-circuit dice are located in a memory package, a memory module, a memory card or a solid-state drive.