Semiconductor device

Abstract

A microcomputer includes a bus, a CPU (Central Processing Unit) coupled to the bus, a RAM (Random-access Memory) coupled to the bus, and an AD (Analog-to-Digital) converter coupled to the bus. The AD converter includes a switching circuit for switching between an analog signal and a reference potential, a first DA (Digital-to-Analog) converter including a plurality of first capacitors each having one end that can be individually coupled to the switching circuit and the other end coupled to a common output line, one or a plurality of testing capacitors that are dedicated for testing, each having one end to which the reference potential or a potential obtained by dividing the reference potential can be individually inputted, and a control circuit. In a normal mode, the control circuit determines a digital value corresponding to the analog signal, based on the output line.

What is claimed is: 
     
         1 . A microcomputer comprising:
 a bus;   a CPU (Central Processing Unit) coupled to the bus;   a RAM (Random-access Memory) coupled to the bus; and   an AD (Analog-to-Digital) converter coupled to the bus,   wherein the AD converter comprises:
 a switching circuit for switching between an analog signal and a reference potential; 
 a first DA (Digital-to-Analog) converter including a plurality of first capacitors each having one end that can be individually coupled to the switching circuit and another end coupled to a common output line; 
 one or a plurality of testing capacitors that are dedicated for testing, each having one end to which the reference potential or a potential obtained by dividing the reference potential can be individually inputted; and 
   a control circuit,   wherein, in a normal mode, the control circuit determines a digital value corresponding to the analog signal, based on the output line, and   wherein, in a test mode, the control circuit determines accuracy of a first capacitor under test by comparing a potential of the output line and a potential of another end of the one or more testing capacitors in a state where the reference potential is inputted to one end of the first capacitor under test.   
     
     
         2 . The microcomputer according to  claim 1 ,
 wherein the AD converter comprises:
 a second DA converter which includes a plurality of resistive elements and outputs a potential obtained by dividing the reference potential by the resistive elements, and 
   wherein the first DA converter comprises:
 a second capacitor having one end for receiving an output potential of the second DA converter and another end coupled to the output line. 
   
     
     
         3 . The microcomputer according to  claim 2 ,
 wherein the AD converter comprises:
 first and second testing capacitors as the one or more testing capacitors, and 
   wherein, in the test mode, the control circuit determines accuracy of the first capacitor under test by comparing a potential of the output line and a potential of another end of the first and second testing capacitors in a state where the reference potential is inputted to one end of the first testing capacitor, a potential obtained by dividing the reference potential is inputted to one end of the second testing capacitor, and the reference potential is inputted to one end of the first capacitor under test.   
     
     
         4 . The microcomputer according to  claim 3 ,
 wherein, in the test mode, the control circuit further determines accuracy of the first capacitor under test by comparing a potential of the output line and a potential of the other end of the first testing capacitor in a state where the reference potential is inputted to one end of the first testing capacitor, a potential obtained by dividing the reference potential is inputted to one end of the second testing capacitor, and the reference potential is inputted to one end of the first capacitor under test.   
     
     
         5 . The microcomputer according to  claim 1 ,
 wherein each of the first capacitors is formed so as to have a same capacitance value,   wherein the AD converter comprises first and second testing capacitors as the one or more testing capacitors,   wherein the first testing capacitor is formed so that a capacitance value thereof is larger than a capacitance value of each first capacitor,   wherein the second testing capacitor is formed so that a capacitance value thereof is smaller than a capacitance value of each first capacitor, and   wherein, in the test mode, the control circuit executes a first determination operation for determining accuracy of the first capacitor under test by comparing a potential of the output line and a potential of another end of the first testing capacitor in a state where the reference potential is inputted to one end of the first testing capacitor and the reference potential is inputted to one end of the first capacitor under test, and executes a second determination operation for determining accuracy of the first capacitor under test by comparing a potential of the output line and a potential of another end of the second testing capacitor in a state where the reference potential is inputted to one end of the second testing capacitor and the reference potential is inputted to one end of the first capacitor under test.   
     
     
         6 . The microcomputer according to  claim 2 ,
 wherein the switching circuit switches among the analog signal, the reference potential, and the output potential of the second DA converter,   wherein the AD converter comprises first and second testing capacitors as the one or more testing capacitors, and   wherein, in the test mode, the control circuit executes a first determination operation for determining accuracy of the first capacitor under test by comparing a potential of the output line and a potential of another end of the first testing capacitor in a state where the reference potential is inputted to one end of the first testing capacitor and a potential obtained by dividing the reference potential is inputted to one end of the first capacitor under test, and executes a second determination operation for determining accuracy of the first capacitor under test by comparing a potential of the output line and a potential of the other end of the first testing capacitor in a state where the a potential obtained by dividing the reference potential is inputted to one end of the first testing capacitor and the reference potential is inputted to one end of the first capacitor under test.