Method of manufacturing semiconductor device, and semiconductor device

Abstract

Provided is a semiconductor device with improved reliability. A logic chip (first semiconductor chip) and a laminated body (second semiconductor chip) are stacked in that order over a wiring substrate. An alignment mark formed over the wiring substrate is aligned with an alignment mark formed on a front surface of the logic chip, whereby the logic chip is mounted over the wiring substrate. An alignment mark formed on a back surface of the logic chip is aligned with an alignment mark formed on a front surface of the laminated body, whereby the laminated body is mounted over the back surface of the logic chip LG.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device, comprising:
 a first semiconductor chip including a first surface, a plurality of first electrodes formed on the first surface, and a first alignment mark formed on the first surface; and   a second semiconductor chip including a second surface, a plurality of second electrodes formed on the second surface, and a second alignment mark formed on the second surface;   wherein the second semiconductor chip is mounted over the first semiconductor chip such that the second surface faces the first surface, and   wherein the plurality of second electrodes are electrically connected with the plurality of first electrodes via a plurality of first terminals, respectively.   
     
     
         22 . The semiconductor device according to  claim 21 ,
 wherein, in plan view, the plurality of first electrodes are formed at a central area of the first surface, and   wherein, in plan view, the plurality of second electrodes are formed at a central area of the second surface.   
     
     
         23 . The semiconductor device according to  claim 22 ,
 wherein, in plan view, the first alignment mark is formed at a peripheral area outside the central area of the first surface, and   wherein, in plan view, the second alignment mark is formed at a peripheral area outside the central area of the second surface.   
     
     
         24 . The semiconductor device according to  claim 23 ,
 wherein, in plan view, a size of the second semiconductor chip is greater than a size of the first semiconductor chip.   
     
     
         25 . The semiconductor device according to  claim 23 ,
 wherein the whole of the first surface of the first semiconductor chip is covered by the second semiconductor chip.   
     
     
         26 . The semiconductor device according to  claim 21 ,
 wherein the first semiconductor chip further includes a third surface opposed to the first surface, and a plurality of third electrodes formed on the third surface,   wherein the plurality of third electrodes are electrically connected with the plurality of first electrodes via a plurality of fourth electrodes, respectively, and   wherein each of the plurality of fourth electrodes penetrates the first semiconductor chip from one of the first surface and the third surface to the other.   
     
     
         27 . The semiconductor device according to  claim 26 ,
 wherein the first semiconductor chip is mounted over a wiring substrate such that the third surface of the first semiconductor chip faces a fourth surface of the wiring substrate, and   wherein the plurality of third electrodes are electrically connected with a plurality of fifth electrodes formed on the fourth surface of the wiring substrate via a plurality of second terminals, respectively.   
     
     
         28 . The semiconductor device according to  claim 21 ,
 wherein the second semiconductor chip is a memory chip, and   wherein the first semiconductor chip is a logic chip controlling the memory chip.