Pitch multiplication spacers and methods of forming the same

Abstract

Spacers in a pitch multiplication process are formed without performing a spacer etch. Rather, the mandrels are formed over a substrate and then the sides of the mandrels are reacted, e.g., in an oxidization, nitridation, or silicidation step, to form a material that can be selectively removed relative to the unreacted portions of the mandrel. The unreacted portions are selectively removed to leave a pattern of free-standing spacers. The free-standing spacers can serve as a mask for subsequent processing steps, such as etching the substrate.

1 - 14 . (canceled) 
     
     
         15 . An intermediate mask pattern overlying a partially fabricated integrated circuit, comprising:
 a plurality of spaced mandrels formed of a mandrel material;   a cap layer overlying a top surface of each of the mandrels;   a layer of pre-spacer material overlying each cap layer; and   spacers on sides of each of the mandrels, wherein the spacers comprise a combination of the pre-spacer material and the mandrel material, wherein the pre-spacer material extends between neighboring spacers.   
     
     
         16 . The intermediate mask pattern of  claim 15 , wherein the cap layer comprises silicon oxide or silicon nitride. 
     
     
         17 . The intermediate mask pattern of  claim 15 , wherein the mandrel comprises silicon. 
     
     
         18 . The intermediate mask pattern of  claim 15 , wherein the spacers comprise a metal silicide. 
     
     
         19 . The intermediate mask pattern of  claim 18 , wherein the metal of the metal silicide is selected from the group consisting of tantalum, hafnium, and nickel. 
     
     
         20 . The intermediate mask pattern of  claim 15 , wherein the spacers are sublithographic features. 
     
     
         21 . The intermediate mask pattern of  claim 15 , wherein the spacers have a separation of 80 nm or less. 
     
     
         22 . The intermediate mask pattern of  claim 21 , wherein the separation is 50 nm or less. 
     
     
         23 . The intermediate mask pattern of  claim 18 , wherein the spacers comprise a metal silicide. 
     
     
         24 . The intermediate mask pattern of  claim 15 , wherein the layer of spacer material extends continuously over the plurality of spaced mandrels. 
     
     
         25 . The intermediate mask pattern of  claim 15 , further comprising:
 a hard mask layer underlying the spacers; and   a substrate underlying the hard mask layer.   
     
     
         26 . The intermediate mask pattern of  claim 25 , wherein the substrate is a silicon wafer. 
     
     
         27 . The intermediate mask pattern of  claim 25 , wherein the hard mask layer comprises silicon. 
     
     
         28 . The intermediate mask pattern of  claim 27 , wherein the hard mask layer comprises silicon oxide. 
     
     
         29 . The intermediate mask pattern of  claim 28 , further comprising an amorphous layer between the hard mask layer and the substrate. 
     
     
         30 . The intermediate mask pattern of  claim 15 , wherein the mandrels have a width of 120 nm of less. 
     
     
         31 . The intermediate mask pattern of  claim 30 , wherein the mandrels have a width of 80 nm or less. 
     
     
         32 . The intermediate mask pattern of  claim 15 , wherein the partially fabricated integrated circuit is a partially formed memory. 
     
     
         33 . The intermediate mask pattern of  claim 15 , wherein the memory is flash memory. 
     
     
         34 . The intermediate mask pattern of  claim 15 , wherein the partially fabricated integrated circuit is a partially formed processor.