Bus connection circuit, semiconductor device and operation method of bus connection circuit for making procedure for switching between a 1-cycle transfer and a 2-cycle transfer unnecessary

Abstract

A bus connection circuit connects a bus master and a plurality of bus slaves. The bus connection circuit includes a minor area access detecting circuit and a processing circuit. The minor area access detecting circuit detects that the bus master accesses a minor area of a first bus slave of the plurality of bus slaves, and output a detection signal based on a detection result. The processing circuit executes processing preset in correspondence to the detection result, to an area or data as an access object, based on the detection result.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a bus master;   a plurality of bus slaves;   a bus connection circuit configured to couple said bus master and said plurality of bus slaves; and   a processing circuit configured to transfer read data from a source bus slave of said plurality of bus slaves to a destination bus slave of said plurality of bus slaves without passing through said bus master;   wherein said bus master sets an access to a mirror area of said source bus slave and a write request in case of direct transfer from said source bus slave to said destination bus slave,   wherein said bus connection circuit comprises a mirror area access detecting circuit configured to detect that said bus master accesses the mirror area, and output a detection signal based on a detection result,   wherein said processing circuit further comprises a write-read conversion circuit configured to convert the write request into a read request, when detecting the access to said mirror area from said bus master, and   wherein said write-read conversion circuit comprises:
 an address decoder configured to decode said access to said mirror area and output a decode result; 
 a logic gate configured to receive said decode result, a bus slave select signal, and a transfer enable signal; and 
 a selector configured to select a logic state of input strobe signal based on an output of said logic gate. 
   
     
     
         2 . The semiconductor device according to  claim 1 ,
 wherein said logic gate is AND gate.   
     
     
         3 . The semiconductor device according to  claim 1 ,
 wherein said selector selects a same logic state with the input strobe signal when said access is to the minor area.