Tunable Stressed Polycrystalline Silicon on Dielectrics in an Integrated Circuit

Abstract

A method of forming an integrated circuit device is disclosed. A polycrystalline silicon layer is formed in direct contact with a dielectric material so that the dielectric material induces a stress in the polycrystalline silicon layer as the polycrystalline silicon layer is formed. A MOS transistor that includes a gate comprising the polycrystalline silicon is then completed.

What is claimed is: 
     
         1 . A method of forming an integrated circuit device, the method comprising:
 forming a dielectric material;   forming a polycrystalline silicon layer in direct contact with the dielectric material so that the dielectric material induces a stress in the polycrystalline silicon layer as the polycrystalline silicon layer is formed; and   completing formation of a MOS transistor that includes a gate comprising the polycrystalline silicon.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a gate structure over a semiconductor body; and   etching a channel in the gate structure, wherein forming the dielectric material comprises forming the dielectric material within the channel.   
     
     
         3 . The method of  claim 2 , wherein forming the gate structure comprises forming a sacrificial gate region and forming sidewalls adjacent the sacrificial gate region and wherein forming the channel comprises removing the sacrificial gate region. 
     
     
         4 . The method of  claim 1 , wherein the MOS transistor is an n-channel MOSFET transistor and wherein the dielectric material comprises mullite (3Al 2 O 3 .2SiO 2 ). 
     
     
         5 . The method of  claim 1 , wherein the MOS transistor is an n-channel MOSFET transistor and wherein the dielectric material comprises alumina (Al 2 O 3 ). 
     
     
         6 . The method of  claim 1 , wherein the MOS transistor is an n-channel MOSFET, the polycrystalline silicon has a compressive stress, and a tensile stress is induced in a channel of the MOS transistor. 
     
     
         7 . The method of  claim 1 , wherein the MOS transistor is a p-channel MOSFET transistor and wherein the dielectric comprises silicon aluminum oxynitride (SiAlON). 
     
     
         8 . The method of  claim 1 , wherein the MOS transistor is a p-channel MOSFET transistor, the polycrystalline silicon has a tensile stress, and a compressive stress is induced in a channel of the transistor. 
     
     
         9 . The method of  claim 1 , wherein forming the dielectric material comprises depositing a gate dielectric layer over a semiconductor body, the gate dielectric layer comprising a material with a high dielectric constant. 
     
     
         10 . The method of  claim 9 , wherein the gate dielectric comprises an aluminum compound. 
     
     
         11 . The method of  claim 9 , wherein the gate dielectric comprises an oxynitride. 
     
     
         12 . A method of manufacturing an integrated circuit device, the method comprising:
 etching a channel in a substrate of the integrated circuit device;   depositing a layer of dielectric material on sidewalls within the channel; and   depositing polycrystalline silicon over the dielectric material layer within the channel, wherein stress is induced in the polycrystalline silicon by the dielectric material as the polycrystalline silicon is being deposited.   
     
     
         13 . The method of  claim 12 , wherein the dielectric comprises mullite (3Al 2 O 3 .2SiO 2 ). 
     
     
         14 . The method of  claim 12 , wherein the dielectric comprises alumina (Al 2 O 3 ). 
     
     
         15 . The method of  claim 12 , wherein the dielectric comprises a silicon aluminum oxynitride (SiAlON). 
     
     
         16 . The method of  claim 12 , wherein the stress induced in the polycrystalline silicon causes the substrate to bend to counteract a warp in the substrate. 
     
     
         17 . A transistor, comprising:
 a gate dielectric layer overlying a semiconductor body;   an outer sidewall region overlying the gate dielectric;   an inner sidewall layer overlying the gate dielectric adjacent inner sidewalls of the outer sidewall region, the inner sidewall layer comprising a material selected from the group consisting of silicon aluminum oxynitride (SiAlON), mullite (3Al 2 O 3 .2SiO 2 ), and alumina (Al 2 O 3 ); and   polycrystalline silicon overlying the gate dielectric layer and in physical contact with the inner sidewall layer.   
     
     
         18 . The transistor of  claim 17 , wherein transistor is an n-channel MOSFET transistor and wherein the inner sidewall layer comprises mullite (3Al 2 O 3 .2SiO 2 ). 
     
     
         19 . The transistor of  claim 17 , wherein transistor is an n-channel MOSFET transistor and wherein the inner sidewall layer comprises alumina (Al 2 O 3 ). 
     
     
         20 . The transistor of  claim 17 , wherein the transistor is a p-channel MOSFET transistor, and wherein the inner sidewall layer comprises silicon aluminum oxynitride (SiAlON).