Structure and method to obtain eot scaled dielectric stacks

Abstract

Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

What is claimed is: 
     
         1 . A method of forming a semiconductor structure comprising:
 incorporating at least one pFET threshold voltage adjusting element into an interfacial layer of at least one patterned gate stack including a high k gate dielectric, a metallic electrode and a Si-containing electrode, wherein said incorporating modifies the interfacial layer into a modified interfacial layer containing said pFET threshold voltage adjusting element, and wherein said incorporating comprises diffusion of said pFET threshold voltage adjusting element from a metallic electrode which includes said pFET threshold voltage adjusting element embedded therein.   
     
     
         2 . The method of  claim 1 , wherein said modified interfacial layer comprising a reaction product of a semiconductor material and said pFET threshold voltage adjusting element. 
     
     
         3 . The method of  claim 2 , wherein said semiconductor material is selected from a semiconductor oxide, a semiconductor nitride and a nitrided semiconductor. 
     
     
         4 . The method of  claim 1  wherein said pFET threshold voltage adjusting element is selected from the group consisting of Al, Ge, Ti, Ni, Co, Tl and Ta. 
     
     
         5 . The method of  claim 1 , wherein said incorporating said pFET voltage adjusting material comprises annealing. 
     
     
         6 . The method of  claim 5 , wherein said annealing is performed after forming said metallic electrode. 
     
     
         7 . The method of  claim 5 , wherein said annealing is performed at a temperature from 500° C. to 1100° C. 
     
     
         8 . The method of  claim 1 , wherein said incorporating occurs during forming said metallic electrode. 
     
     
         9 . The method of  claim 1 , wherein said modified interfacial layer, said high k gate dielectric, said metallic electrode and said Si-containing electrode have sidewalls that are vertically coincident to each other. 
     
     
         10 . The method of  claim 1 , wherein said metallic electrode has a bottommost surface that directly contacts a topmost surface of said high k gate dielectric.