Semiconductor package with a semiconductor die embedded within substrates

Abstract

Embodiments of the present disclosure provide configurations for a semiconductor package and associated methods of fabricating the semiconductor package. A method of fabricating a semiconductor package includes attaching a semiconductor die to a first substrate, attaching a second substrate to the first substrate, wherein the semiconductor die is embedded in between the first substrate and the second substrate, and forming an electrically insulative structure to substantially encapsulate the semiconductor die, wherein forming the electrically insulative structure is performed subsequent to the second substrate being attached to the first substrate. Additional embodiments may be described and/or claimed.

What is claimed is: 
     
         1 . A semiconductor package comprising:
 a first substrate;   a semiconductor die disposed on the first substrate; and   a second substrate coupled to the first substrate such that the semiconductor die is disposed between the first substrate and the second substrate, wherein the second substrate comprises
 (i) a first C-stage material that is converted from a B-stage prepreg material, wherein the first C-stage material is configured to form an electrically insulative structure that substantially encapsulates the semiconductor die, and 
 (ii) a second C-stage material disposed on the first C-stage material. 
   
     
     
         2 . The semiconductor package of  claim 1 , wherein the second C-stage material has a coefficient of thermal expansion that is substantially the same as a coefficient of thermal expansion of material used to fabricate the first substrate. 
     
     
         3 . The semiconductor package of  claim 1 , further comprising:
 one or more interconnect bumps configured to couple the semiconductor die to the first substrate.   
     
     
         4 . The semiconductor package of  claim 3 , further comprising:
 traces formed on opposing surfaces of the first substrate;   one or more vias formed in the first substrate to electrically couple the traces formed on the opposing surfaces of the first substrate; and   one or more solder balls coupled to the first substrate to provide an electrical connection with an electronic device external to the semiconductor package.   
     
     
         5 . The semiconductor package of  claim 4 , wherein the semiconductor die is electrically coupled to the electronic device external to the semiconductor package via (i) a first interconnect bump of the one or more interconnect bumps, (ii) a first trace formed on a first surface of the first substrate, (iii) a first via of the one or more vias formed in the first substrate, (iv) a second trace formed on a second surface of the first substrate, and (v) a first solder ball of the one or more solder balls coupled to the first substrate. 
     
     
         6 . The semiconductor package of  claim 1 , wherein the first C-stage material is converted from the B-stage prepreg material, subsequent to the B-stage prepreg material being deposited on the first substrate to substantially surround the semiconductor die. 
     
     
         7 . The semiconductor package of  claim 1 , further comprising:
 one or more vias formed through the first C-stage material and the second C-stage material; and   a build-up layer formed on the second C-stage material, wherein the build-up layer includes features to route electrical signals to or from the first substrate through the one or more vias.   
     
     
         8 . The semiconductor package of  claim 1 , wherein:
 the first substrate includes a core comprising polyimide.   
     
     
         9 . The semiconductor package of  claim 1 , wherein the B-stage prepreg material is converted to the first C-stage material by fusing the B-stage prepreg material. 
     
     
         10 . The semiconductor package of  claim 1 , wherein the first substrate comprises electrically insulative material. 
     
     
         11 . The semiconductor package of  claim 1 , wherein the B-stage prepreg material comprises fusible materials pre-impregnated with resin. 
     
     
         12 . The semiconductor package of  claim 1 , wherein the B-stage prepreg material comprises intermediate stage thermosetting resins. 
     
     
         13 . The semiconductor package of  claim 1 , wherein the second C-stage material deposited on the B-stage prepreg material facilitates in reduction of warping of the second substrate, while curing the B-stage prepreg material to convert the B-stage prepreg material to the first C-stage material. 
     
     
         14 . The semiconductor package of  claim 1 , wherein a surface of the second substrate is directly attached to a surface of the first substrate. 
     
     
         15 . The semiconductor package of  claim 1 , further comprising:
 one or more vias formed in the second substrate to provide an electrical connection between (i) a surface of the second substrate that is not facing the first substrate and (ii) a surface of the first substrate that is facing the second substrate.