Structure and method to obtain eot scaled dielectric stacks

Abstract

Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

What is claimed is: 
     
         1 . A method of forming a semiconductor structure comprising:
 incorporating at least one high k material dopant element into an interfacial layer of at least one patterned gate stack including a high k gate dielectric, a metallic electrode and a Si-containing electrode, wherein said incorporating modifies the interfacial layer into a modified interfacial layer having at least said at least one high k material dopant element incorporated therein, and said incorporating said at least one high k material dopant element includes diffusion of said high k material dopant element from an overlying interfacial scaling material layer.   
     
     
         2 . The method of  claim 1 , wherein said at least one high k material dopant element is selected from an nFET threshold voltage adjusting element and a pFET threshold voltage element. 
     
     
         3 . The method of  claim 1 , wherein said overlying interfacial scaling material layer is located directly on an upper surface of the interfacial layer. 
     
     
         4 . The method of  claim 1 , wherein said overlying interfacial scaling material layer is located directly on an upper surface of the high k gate dielectric. 
     
     
         5 . The method of  claim 1 , wherein said overlying interfacial scaling material is located directly on an upper surface of said metallic electrode. 
     
     
         6 . The method of  claim 1 , wherein said modified interfacial layer comprises a reaction product of a semiconductor material and at least one high k material dopant element. 
     
     
         7 . The method of  claim 6 , wherein said semiconductor material is selected from a semiconductor oxide, a semiconductor nitride and a nitrided semiconductor, and said at least one high k material dopant element is an nFET threshold voltage adjusting element. 
     
     
         8 . The method of  claim 6 , wherein said semiconductor material is selected from a semiconductor oxide, a semiconductor nitride and a nitrided semiconductor, and said at least one high k material dopant element is a pFET threshold voltage adjusting element. 
     
     
         9 . The method of  claim 1 , wherein said at least one high k material dopant element is an nFET threshold voltage element, and said nFET threshold voltage adjusting element is a rare earth metal. 
     
     
         10 . The method of  claim 1 , wherein said at least one high k material dopant element is an nFET threshold voltage element, and said nFET threshold voltage adjusting element is an alkaline earth metal. 
     
     
         11 . The method of  claim 1 , wherein said at least one high k material dopant element is a pFET threshold voltage element, and said pFET threshold voltage adjusting element includes Al, Ge, Ti, Ni, Co, Tl or Ta. 
     
     
         12 . The method of  claim 1 , wherein said interfacial scaling material layer is completely consumed after said incorporating. 
     
     
         13 . The method of  claim 1 , wherein said interfacial scaling material layer is partially consumed after said incorporating. 
     
     
         14 . The method of  claim 1 , wherein said incorporating said at least one high k material dopant element comprises annealing. 
     
     
         15 . The method of  claim 14 , wherein said annealing is performed after forming said interfacial scaling material layer. 
     
     
         16 . The method of  claim 14 , wherein said annealing is performed at a temperature from 500° C. to 1100° C. 
     
     
         17 . The method of  claim 14 , wherein said annealing is formed after forming one of said high k gate dielectric, said metallic electrode and said Si-containing electrode. 
     
     
         18 . The method of  claim 1 , wherein said incorporating occurs during forming one of said metallic electrode and said Si-containing electrode.