Static Power Reduction in Caches Using Deterministic Naps

Abstract

The dNap architecture is able to accurately transition cache lines to full power state before an access to them. This ensures that there are no additional delays due to waking up drowsy lines. Only cache lines that are determined by the DMC to be accessed in the immediate future are fully powered while others are put in drowsy mode. As a result, we are able to significantly reduce leakage power with no cache performance degradation and minimal hardware overhead, especially at higher associativities. Up to 92% static/Leakage power savings are accomplished with minimal hardware overhead and no performance tradeoff.

What is claimed is: 
     
         1 . A cache memory system, comprising:
 a cache memory operable to store data in a plurality of locations defined by a plurality of addresses and divided into a plurality of cache ways;   a memory nap controller operable to track in-flight cache accesses and further operable to control the desired power state of a plurality of data RAM lines;   a processing block operable to group a plurality of contiguous cache lines into a single power group.   
     
     
         2 . The cache memory system of  claim 1 , wherein:
 the power state of said data RAM lines is determined by the memory nap controller based on all current an outstanding data RAM accesses in all pipeline stages and buffers.   
     
     
         3 . The cache memory system of  claim 1 , wherein:
 the memory nap controller is operable to transition the data RAM lines to a fully powered operating state or to a low power nap state.   
     
     
         4 . The cache memory system of  claim 1 , wherein:
 the memory nap controller is operable to complete the transition of the data RAM lines to a fully powered state ahead of the actual data RAM access without any additional latency incurred at the time of the access.   
     
     
         5 . The cache memory system of  claim 1 , wherein:
 the memory nap controller is operable to place the cache lines that will not be used in the immediate future in a low power state, and keep only the cache lines determined to be accessed in the immediate future in a fully powered on state.   
     
     
         6 . The cache memory system of  claim 1 , wherein:
 the memory nap controller is operable, after a hit/miss determination has selected a single cache way to place all other ways in a low power state.   
     
     
         7 . The cache memory system of  claim 6 , wherein:
 the memory nap controller will, in the case of a new access to a cache way that is transitioning to a low power state maintain said cache way in a powered up state until the access has completed.