Pulse output circuit, display device, and electronic device

Abstract

An object of the present invention is to suppress deterioration in the thin film transistor. A plurality of pulse output circuits each include first to eleventh thin film transistors is formed. The pulse output circuit is operated on the basis of a plurality of clock signals which control each transistor, the previous stage signal input from a pulse output circuit in the previous stage, the next stage signal input from a pulse output circuit in the next stage, and a reset signal. In addition, a microcrystalline semiconductor is used for a semiconductor layer serving as a channel region of each transistor. Therefore, degradation of characteristics of the transistor can be suppressed.

1 . (canceled) 
     
     
         2 . A driver circuit comprising:
 a first transistor;   a second transistor;   a third transistor;   a fourth transistor;   a fifth transistor;   a sixth transistor;   a seventh transistor; and   an eighth transistor,   wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,   wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,   wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,   wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,   wherein a gate of the third transistor is electrically connected to a first line,   wherein the other of the source and the drain of the fifth transistor is electrically connected to a second line,   wherein a gate of the fourth transistor is electrically connected to a gate of the sixth transistor,   wherein a gate of the seventh transistor is electrically connected to the gate of the second transistor,   wherein one of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the seventh transistor,   wherein the other of the source and the drain of the second transistor is electrically connected to a third line, and   wherein the other of the source and the drain of the seventh transistor is electrically connected to the third line.   
     
     
         3 . The driver circuit according to  claim 2 ,
 wherein the gate of the fourth transistor is directly connected to the gate of the sixth transistor.   
     
     
         4 . The driver circuit according to  claim 2 ,
 wherein the gate of the eighth transistor is electrically connected to the gate of the first transistor.   
     
     
         5 . The driver circuit according to  claim 2 ,
 wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the first transistor.   
     
     
         6 . The driver circuit according to  claim 2 ,
 wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the fourth transistor.   
     
     
         7 . The driver circuit according to  claim 2 ,
 wherein the other of the source and the drain of the fifth transistor is directly connected to the second line.   
     
     
         8 . The driver circuit according to  claim 2 , further comprising a ninth transistor,
 wherein a gate of the ninth transistor is electrically connected to the gate of the second transistor, and   wherein one of a source and a drain of the ninth transistor is electrically connected to the other of the source and the drain of the third transistor.   
     
     
         9 . The driver circuit according to  claim 2 , further comprising a tenth transistor,
 wherein one of a source and a drain of the tenth transistor is electrically connected to the one of the source and the drain of the seventh transistor, and   wherein the other of the source and the drain of the tenth transistor is electrically connected to the third transistor.   
     
     
         10 . A driver circuit comprising:
 a shift register comprising:
 a first stage; and
 a second stage comprising: 
 a first transistor; 
 a second transistor; 
 a third transistor; 
 a fourth transistor; 
 a fifth transistor; 
 a sixth transistor; 
 a seventh transistor; and 
 an eighth transistor, 
 
   wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,   wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,   wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,   wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,   wherein a gate of the third transistor is electrically connected to a first line,   wherein the other of the source and the drain of the fifth transistor is electrically connected to a second line,   wherein a signal output from the first stage is input to a gate of the fourth transistor,   wherein the signal output from the first stage is input to a gate of the sixth transistor,   wherein a gate of the seventh transistor is electrically connected to the gate of the second transistor,   wherein one of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the seventh transistor,   wherein the other of the source and the drain of the second transistor is electrically connected to a third line, and   wherein the other of the source and the drain of the seventh transistor is electrically connected to the third line.   
     
     
         11 . The driver circuit according to  claim 10 ,
 wherein the gate of the fourth transistor is directly connected to the gate of the sixth transistor.   
     
     
         12 . The driver circuit according to  claim 10 ,
 wherein the gate of the eighth transistor is electrically connected to the gate of the first transistor.   
     
     
         13 . The driver circuit according to  claim 10 ,
 wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the first transistor.   
     
     
         14 . The driver circuit according to  claim 10 ,
 wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the fourth transistor.   
     
     
         15 . The driver circuit according to  claim 10 ,
 wherein the other of the source and the drain of the fifth transistor is directly connected to the second line.   
     
     
         16 . The driver circuit according to  claim 10 , further comprising a ninth transistor,
 wherein a gate of the ninth transistor is electrically connected to the gate of the second transistor, and   wherein one of a source and a drain of the ninth transistor is electrically connected to the other of the source and the drain of the third transistor.   
     
     
         17 . The driver circuit according to  claim 10 , further comprising a tenth transistor,
 wherein one of a source and a drain of the tenth transistor is electrically connected to the one of the source and the drain of the seventh transistor, and   wherein the other of the source and the drain of the tenth transistor is electrically connected to the third transistor.   
     
     
         18 . A display device comprising:
 a pixel portion; and   a gate driver electrically connected to the pixel portion, the gate driver comprising a shift register comprising:
 a first stage; and
 a second stage comprising: 
 a first transistor; 
 a second transistor; 
 a third transistor; 
 a fourth transistor; 
 a fifth transistor; 
 a sixth transistor; 
 a seventh transistor; and 
 an eighth transistor, 
 
   wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor,   wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,   wherein one of a source and a drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,   wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor,   wherein a gate of the third transistor is electrically connected to a first line,   wherein the other of the source and the drain of the fifth transistor is electrically connected to a second line,   wherein a signal output from the first stage is input to a gate of the fourth transistor,   wherein the signal output from the first stage is input to a gate of the sixth transistor,   wherein a gate of the seventh transistor is electrically connected to the gate of the second transistor,   wherein one of a source and a drain of the eighth transistor is electrically connected to one of a source and a drain of the seventh transistor,   wherein the other of the source and the drain of the second transistor is electrically connected to a third line, and   wherein the other of the source and the drain of the seventh transistor is electrically connected to the third line.   
     
     
         19 . The display device according to  claims 18 ,
 wherein the gate of the fourth transistor is directly connected to the gate of the sixth transistor.   
     
     
         20 . The display device according to  claim 18 ,
 wherein the gate of the eighth transistor is electrically connected to the gate of the first transistor.   
     
     
         21 . The display device according to  claim 18 ,
 wherein the other of the source and the drain of the eighth transistor is electrically connected to the other of the source and the drain of the first transistor.   
     
     
         22 . The display device according to  claim 18 ,
 wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the fourth transistor.   
     
     
         23 . The display device according to  claim 18 ,
 wherein the other of the source and the drain of the fifth transistor is directly connected to the second line.   
     
     
         24 . The display device according to  claim 18 , further comprising a ninth transistor,
 wherein a gate of the ninth transistor is electrically connected to the gate of the second transistor, and   wherein one of a source and a drain of the ninth transistor is electrically connected to the other of the source and the drain of the third transistor.   
     
     
         25 . The display device according to  claim 18 , further comprising a tenth transistor,
 wherein one of a source and a drain of the tenth transistor is electrically connected to the one of the source and the drain of the seventh transistor, and   wherein the other of the source and the drain of the tenth transistor is electrically connected to the third transistor.