Semiconductor device having a serial communication circuit for a host unit

Abstract

In a serial communication circuit, a data extracting section extracts reception data based on a reception clock signal with maximum speed. A pattern determining section compares a reception bit pattern of the reception data corresponding to a characteristic pattern and each of a plurality of detection bit patterns for the characteristic pattern, and indicates when the reception bit pattern matches one of the detection bit patterns. A periodicity determining section determines a period when the reception bit pattern matches the detection bit pattern, based on the pattern match indication, detects that the detection bit pattern emerges continuously in a stream of the reception data every the period, and determines a generation difference between transmission and reception speeds based on the detection bit pattern. A transmission rate setting section determines the transmission speed of a connected device transmitting the reception data based on the generation difference and maximum speed.

What is claimed is: 
     
         1 . A semiconductor device comprising a serial communication circuit for a host unit which comprises:
 a data extracting section configured to   i) receive a) an input data signal comprising a clock signal and reception data corresponding to a characteristic pattern, the input data signal transmitted at a transmission speed from a connected device unit, and b) a reference reception clock signal at a maximum speed,   ii) based on the maximum speed of the reference reception clock signal, extract the reception data and a reception recovery clock signal from the input data signal, and   iii) output an output data signal and the reception recovery clock signal;   a pattern determining section configured to   i) receive the reception recovery clock signal from the data extracting section and to receive the input data signal, and   ii) based on a speed of the reception recovery clock signal, compare a reception bit pattern of the reception data with each of a plurality of detection bit pattern for said characteristic pattern, and provide a notice of pattern matching when each bit of said reception bit pattern matches corresponding bits of one of said plurality of detection bit patterns;   a periodicity determining section operatively connected to an output of the pattern determining section and configured to determine a period when said reception bit pattern, bit by bit, matches said detection bit pattern, based on the notice from said pattern determining section, detect that said detection bit pattern emerges continuously in a stream of the reception data every said determined period, and determine a generation difference between the transmission speed and a reception speed based on said detection bit pattern; and   a transmission rate setting section configured to determine said transmission speed of the connected device which transmits the reception data, based on said generation difference and said maximum speed.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein said plurality of detection bit patterns are patterns generated by linking each of bits of said characteristic pattern of original data indicating a bit pattern transmitted in speed negotiation for 2 n , and n indicates each of integers from “0” to a maximum generation difference. 
     
     
         3 . The semiconductor device according to  claim 2 , wherein said periodicity determining section determines said generation difference when detecting that said detection bit pattern emerges periodically and continuously more than a predetermined number of times. 
     
     
         4 . The semiconductor device according to  claim 2 , wherein said characteristic pattern is a 40-bit bit pattern of ALIGN data. 
     
     
         5 . The semiconductor device according to  claim 2 , wherein said characteristic pattern is a bit pattern matching to a part of a 40-bit bit pattern of ALIGN data and not matching to the other part thereof. 
     
     
         6 . The semiconductor device according to  claim 5 , wherein said characteristic pattern is a bit pattern indicating K28.5 code or D27.3 code of the ALIGN data. 
     
     
         7 . The semiconductor device according to  claim 5 , wherein said characteristic pattern is a bit pattern obtained by connecting a pattern of D10.2 code of the ALIGN data pattern and a 2-bit head pattern of D27.3 code, or a 15-bit pattern obtained by continuously connecting a bit alternatively showing “1” and “0” for 1 bit, 2 bits, 3 bits, 4 bits and 5 bits. 
     
     
         8 . The semiconductor device according to  claim 5 , wherein said characteristic pattern is a bit pattern obtained by connecting a longest continuing pattern of “1” and “0” and one bit on a front side and back side of the longest continuing pattern, of the 40-bit bit pattern of the ALIGN data.