Substrate structure and manufacturing method thereof

Abstract

A substrate structure including a carrier and a substrate is provided. The carrier includes a release layer, a dielectric layer and a metal layer. The dielectric layer is disposed between the release layer and the metal layer. The substrate includes a packaging region and a peripheral region. The peripheral region is connected to the packaging region and surrounds the packaging region. The peripheral region or the packaging region has a plurality of through holes. The substrate is disposed on the carrier. The release layer is located between the substrate and the dielectric layer. The release layer and the dielectric layer are filled in the through hole such that the substrate is separably attached to the carrier.

What is claimed is: 
     
         1 . A substrate structure, comprising:
 a carrier, comprising a release layer, a dielectric layer, and a metal layer, wherein the dielectric layer is disposed between the release layer and the metal layer; and   a substrate, comprising a packaging region and a peripheral region, wherein the peripheral region is connected to the packaging region and surrounds the packaging region, the peripheral region has a plurality of through holes, the substrate is disposed on the carrier, the release layer is located between the substrate and the dielectric layer, and the release layer and the dielectric layer are filled into the through holes, such that the substrate is separably attached to the carrier.   
     
     
         2 . The substrate structure as claimed in  claim 1 , wherein a material of the release layer comprises an aluminum foil or a polyimide (PI) film. 
     
     
         3 . The substrate structure as claimed in  claim 1 , wherein the substrate is a single-layer circuit board. 
     
     
         4 . The substrate structure as claimed in  claim 1 , wherein the substrate is a multi-layer circuit board. 
     
     
         5 . The substrate structure as claimed in  claim 1 , wherein the substrate further comprises a plurality of pads and a patterned solder mask, the pads are disposed on an upper surface of the substrate and located within the packaging region, and the patterned solder mask covers the upper surface and exposes the pads. 
     
     
         6 . The substrate structure as claimed in  claim 5 , wherein the substrate comprises a surface finishing layer covering the pads. 
     
     
         7 . A manufacturing method of a substrate structure, comprising:
 providing a substrate, the substrate comprising a packaging region and a peripheral region, wherein the peripheral region is connected to the packaging region and surrounds the packaging region;   forming a plurality of through holes at the peripheral region;   providing a carrier, wherein the carrier comprises a release layer, a dielectric layer, and a metal layer, and the dielectric layer is disposed between the release layer and the metal layer; and   laminating the substrate onto the release layer of the carrier, such that the release layer and the dielectric layer are filled into the through holes to separably attach the substrate to the carrier.   
     
     
         8 . The manufacturing method of the substrate structure as claimed in  claim 7 , wherein the substrate is a single-layer circuit board. 
     
     
         9 . The manufacturing method of the substrate structure as claimed in  claim 7 , wherein the substrate is a multi-layer circuit board. 
     
     
         10 . The manufacturing method of the substrate structure as claimed in  claim 7 , wherein the step of providing the substrate further comprises:
 forming a plurality of pads on an upper surface of the substrate, and the pads being located within the packaging region; and   forming a patterned solder mask on the upper surface, and the patterned solder mask exposing the pads.   
     
     
         11 . The manufacturing method of the substrate structure as claimed in  claim 10 , wherein the step of providing the substrate further comprises:
 forming a surface finishing layer covering the pads.   
     
     
         12 . A substrate structure, comprising:
 a carrier, comprising a release layer, a dielectric layer, and a metal layer, wherein the dielectric layer is disposed between the release layer and the metal layer; and   a substrate, comprising a packaging region and a peripheral region, wherein the peripheral region is connected to the packaging region and surrounds the packaging region, the packaging region has a plurality of through holes, the substrate is disposed on the carrier, the release layer is located between the substrate and the dielectric layer, and the release layer and the dielectric layer are filled into the through holes located at the packaging region, such that the substrate is separably attached to the carrier.   
     
     
         13 . The substrate structure as claimed in  claim 12 , wherein the substrate further comprises a plurality of pads and a patterned solder mask, the pads are disposed on an upper surface of the substrate and located within the packaging region, the pads are disposed around the through holes, and the patterned solder mask covers the upper surface and exposes the pads. 
     
     
         14 . The substrate structure as claimed in  claim 12 , further comprising a chip disposed in the packaging region and covering one of the through holes to contact the release layer, wherein the chip is electrically connected to the pads by a plurality of wires. 
     
     
         15 . The substrate structure as claimed in  claim 12 , wherein a material of the release layer comprises an aluminum foil or a polyimide (PI) film. 
     
     
         16 . The substrate structure as claimed in  claim 12 , wherein the substrate is a single-layer circuit board. 
     
     
         17 . The substrate structure as claimed in  claim 12 , wherein the substrate is a multi-layer circuit board. 
     
     
         18 . A manufacturing method of a substrate structure, comprising:
 providing a substrate, comprising a packaging region and a peripheral region, wherein the peripheral region is connected to the packaging region and surrounds the packaging region;   forming a plurality of through holes in the packaging region;   providing a carrier, wherein the carrier comprises a release layer, a dielectric layer, and a metal layer, the dielectric layer being disposed between the release layer and the metal layer; and   laminating the substrate to the release layer of the carrier, such that the release layer and the dielectric layer are filled into the through holes to separably attach the substrate to the carrier.   
     
     
         19 . The manufacturing method of the substrate structure as claimed in  claim 18 , wherein the step of providing the substrate further comprises:
 forming a plurality of pads on an upper surface of the substrate, the pads being located in the packaging region and disposed around the through holes; and   forming a patterned solder mask on the upper surface, and the patterned solder mask exposing the pads.   
     
     
         20 . The manufacturing method of the substrate structure as claimed in  claim 19 , further comprising:
 disposing a chip on the packaging region of the substrate, the chip covering one of the through holes and contacting the release layer; and   electrically connecting the chip to the pads via a plurality of wires.