Latch circuit and display device

Abstract

A latch circuit which can control a drain avalanche effect and improve reliability is provided. The latch circuit includes an input transistor importing a voltage corresponding to “0” or “1” when the scanning voltage is input to a gate, a storage capacitance storing a voltage imported by the input transistor, and having a first electrode and a second electrode, the first electrode is input with a capacitance control signal and the second electrode is connected to a second electrode of the input transistor, a first conduction type first transistor having a gate connected to the second electrode of the input transistor, a second electrode connected to a first output terminal, and a first electrode input with a first latch control signal, and a second conduction type second transistor having a gate connected to the second electrode of the first transistor, a second electrode connected to a second output terminal, and a first electrode input with a second latch control signal.

What is claimed is: 
     
         1 . A latch circuit for holding and latching data when a scanning voltage is input, the circuit comprising:
 an input transistor having first and second electrodes and a gate, the first electrode being applied with a voltage corresponding to “0” or “1”, the input transistor outputting the voltage from the second electrode when the scanning voltage is input to the gate;   a retention capacitance retaining a voltage output by the input transistor, and having a first electrode and a second electrode, the second electrode being applied with a fixed voltage and the first electrode being connected to a second electrode of the input transistor;   a first transistor which is one of n type and p type transistors having a gate connected to the second electrode of the input transistor, a first electrode applied with a first latch control signal and a second electrode connected to a first output terminal;   a second transistor which is the other of n type and p type transistors having a gate connected to the second electrode of the first transistor, a first electrode input with a second latch control signal and a second electrode connected to a second output terminal; and   a diode connected between a first electrode and a second electrode of the first transistor and becomes a conducting state corresponding to a change in a voltage level of the first latch control signal;   wherein voltage levels of the first latch control signal and the second latch control signal are respectively changed at a certain timing, so that a voltage of the first output terminal and a voltage of the second output terminal are changed to a voltage corresponding to “0” or “1” and latched.   
     
     
         2 . The latch circuit according to  claim 1 , wherein, on an assumption that time elapses in a sequence from a time t 1  to a time t 6 , the voltage of the second latch control signal is a second voltage level in a time period up to a time t 1  after a voltage corresponding to “0” data or “1” data is retained in the retention capacitance, changed to a first voltage level from the second voltage level at the time t 1 , and changed to the second voltage level from the first voltage level at the time t 5 ; and
 the voltage of the first latch control signal is an intermediate voltage level between the first voltage level and the second voltage level in a time period up to the time t 2 , changed to the second voltage level from the intermediate voltage level at the time t 2 , changed to the first voltage level from the second voltage level at the time t 3 , and changed to the intermediate voltage level from the first voltage level at the time t 4 . 
 
     
     
         3 . The latch circuit according to  claim 2 , wherein the diode is turned OFF before the time t 2 , and is turned OFF at the time t 3  after becoming a conducting state at the time t 2 ;
 wherein the first transistor is turned OFF before the time t 3 , is turned ON or OFF in accordance with the voltage retained in the retention capacitance at the time t 3 , and turned OFF after the time t 4 ; 
 wherein the second transistor is turned ON in the case where the voltage of the first output terminal is the first voltage level before the time t 1 , or turned OFF in the case where the voltage of the first output terminal is the second voltage level at the time t 1 , and turned ON when the first transistor is turned ON at the time t 3 , or turned OFF when the first transistor is turned OFF at the time t 3 ; 
 wherein the voltage of the first output terminal is changed to a the second voltage level at the time t 2  with the diode conducting and maintained at the first voltage level after being changed to the first voltage level in the case where the first transistor is turned ON at the time t 3 , or maintained at the second voltage level in the case where the first transistor is turned OFF at the time t 3 ; and 
 wherein a voltage of the second output terminal is changed to the first voltage level in the case where the second transistor is turned ON at the time t 1 , or maintained at the first voltage level in the case where the second transistor is turned OFF at the time t 1 , and maintained at the second voltage level after being changed to the second voltage level at the time t 5  in the case where the first transistor is turned ON at the time t 3 , or maintained at the first voltage level in the case where the first transistor is turned OFF at the time t 5 . 
 
     
     
         4 . The latch circuit according to  claim 1 , wherein the diode is formed by a diode-connected transistor as same type as the first transistor. 
     
     
         5 . The latch circuit according to  claim 1 , wherein the diode is formed by a plurality of transistors as same type as the first conduction type transistor connected in series and having commonly connected gates input with the first latch control signal. 
     
     
         6 . A latch circuit for holding and latching data when a scanning voltage is input, the circuit comprising:
 an input transistor having first and second electrodes and a gate, the first electrode being applied with a voltage corresponding to “0” or “1”, the input transistor outputting the voltage from the second electrode when the scanning voltage is input to the gate;   a retention capacitance retaining a voltage output by the input transistor, and having a first electrode and a second electrode, the second electrode being applied with a fixed voltage and the first electrode being connected to a second electrode of the input transistor;   a first transistor which is one of n type and p type transistors having a gate connected to the second electrode of the input transistor, a first electrode and a second electrode connected to a first output terminal;   a second transistor which is the other of n type and p type transistors having a gate connected to the second electrode of the first transistor, a first electrode input with a second latch control signal and a second electrode connected to a second output terminal;   a fourth transistor as same type as the first transistor having a gate input with a third latch control signal, a first electrode input with the first latch control signal and a second electrode connected to the first electrode of the first transistor; and   a diode connected between the second electrode of the first transistor and the first electrode of the fourth transistor, the diode becoming a conducting state corresponding to a change in a voltage level of the first latch control signal;   wherein   voltage levels of the first latch control signal, the second latch control signal and the third latch control signal are respectively changed at a certain timing, so that a voltage of the first output terminal and a voltage of the second output terminal are changed to a voltage corresponding to “0” or “1” and latched.   
     
     
         7 . The latch circuit according to  claim 6 , wherein, on an assumption that time elapses in a sequence from a time t 1  to a time t 6 , the voltage of the second latch control signal is a second voltage level in a time period up to a time t 1  after a voltage corresponding to “0” data or “1” data is retained in the retention capacitance, is changed to a first voltage level from the second voltage level at the time t 1 , and changed to the second voltage level from the first voltage level at time t 5 ;
 the voltage of the first latch control signal is the first voltage level in a time period up to a time t 3 , changed to the second voltage level from the first voltage level at the time t 3 , and changed to the first voltage level from the second voltage level at a time t 4 ; and 
 the voltage of the third latch control signal is the first voltage level in a time period up to a time t 2 , changed to the second voltage level from the first voltage level at the time t 2 , and changed to the first voltage level from the second voltage level at the time t 4 . 
 
     
     
         8 . The latch circuit according to  claim 7 , wherein the diode is turned OFF before the time t 3  and is turned OFF at the time t 4  after becoming the conducting state at the time t 3 ;
 wherein the first transistor is turned OFF after the time t 3  and before the time t 4 , and turned ON or OFF in accordance with the voltage retained in the retention capacitance before the time t 3  and after the time t 4 ; 
 wherein the second transistor is turned ON in the case where the voltage of the first output terminal is the first voltage level before the time t 1 , turned OFF in the case where the voltage of the first output terminal is the second voltage level at the time t 1 , turned ON when the first transistor is turned ON at the time t 4 , and turned OFF when the first transistor is turned OFF at the time t 4 ; 
 wherein the voltage of the first output terminal is changed to the second voltage level with the diode conducting at the time t 3 , and maintained at the first voltage level after being changed to the first voltage level in the case where the first transistor is turned ON at the time t 4 , or maintained at the second voltage level in the case where the first transistor is turned OFF at the time t 3 ; and 
 wherein the voltage of the second output terminal is changed to the first voltage level in the case where the second transistor is switch ON at the time t 1 , or maintained the second voltage level in the case where the second transistor is turned OFF at the time t 1 , and maintained at the second voltage level after being changed to the second voltage level at the time t 5  in the case where the first transistor is turned ON at the time t 3 , or maintained at the first voltage level or the voltage of the second output terminal before the time t 1  in the case where the first transistor is turned OFF at the time t 5 . 
 
     
     
         9 . The latch circuit according to  claim 6 , wherein the diode is formed by a diode-connected transistor as same type as the first transistor. 
     
     
         10 . The latch circuit according to  claim 6 , wherein the diode is formed by a plurality of transistors as same type as the first conduction type transistor connected in series and having commonly connected gates input with the first latch control signal. 
     
     
         11 . The latch circuit according to  claim 6 , wherein the input transistor and the first transistor are formed by a plurality of transistors as same type as the first conduction type transistor connected in series and having commonly connected gates, and the second transistor is formed by a plurality of transistors as same type as the second conduction type transistor connected in series and having commonly connected gates.