Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes: vertical channel layers; a pipe channel layer configured to connect lower ends of the vertical channel layers; and a pipe gate surrounding the pipe channel layer and including a first region, which is in contact with the pipe channel layer and includes a first-type impurity, and remaining second regions including a second-type impurity different from the first type impurity.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, comprising:
 forming a pipe gate comprising a trench filled with a sacrificial layer and including a first region, which is in contact with the trench and includes a first-type impurity, and remaining second regions having a second-type impurity different from the first type impurity;   alternately forming first material layers and second material layers on the pipe gate;   forming channel holes connected to the trench by etching the first material layers and the second material layers;   removing the sacrificial layer exposed in lower surfaces of the channel holes;   forming a memory layer along inner surfaces of the trench and the channel holes; and   forming a channel layer on the memory layer.   
     
     
         2 . The method of  claim 1 , wherein the forming of the pipe gate comprises:
 forming a first conductive layer including the second-type impurity;   forming a mask pattern on the first conductive layer;   forming the trench by etching the first conductive layer with the mask pattern as a barrier;   doping an inner surface of the trench with the first-type impurity with the mask pattern as a barrier; and   filling the trench with the sacrificial layer.   
     
     
         3 . The method of  claim 1 , wherein the forming of the pipe gate comprises:
 forming a first conductive layer including the second-type impurity;   forming a dielectric layer on the first conductive layer;   forming a mask pattern on the dielectric layer;   forming the trench by etching the dielectric layer and the first conductive layer with the mask pattern as a barrier;   removing the mask pattern;   doping an inner surface of the trench with the first-type impurity with the dielectric layer as a barrier; and   filling the trench with the sacrificial layer.   
     
     
         4 . The method of  claim 2 , wherein the first conductive layer including the second-type impurity is formed of an N-type poly silicon layer and the first-type impurity is a P-type impurity. 
     
     
         5 . The method of  claim 2 , wherein the forming of the pipe gate further comprises forming a second conductive layer including the first-type impurity on the first conductive layer filled with the sacrificial layer. 
     
     
         6 . The method of  claim 5 , wherein the second conductive layer including the first-type impurity is formed of a poly silicon layer including a P-type impurity. 
     
     
         7 . The method of  claim 6 , wherein the forming of the pipe gate further comprising:
 etching the second conductive layer and the first conductive layer to form the pipe gate, wherein the pipe gate includes the first conductive layer including the trench filled with the sacrificial layer and the second conductive layer, and is located in a cell region.   
     
     
         8 . The method of  claim 7 , wherein in the forming of the pipe gate, a gate electrode is simultaneously formed, wherein the gate electrode includes the first conductive layer including the second-type impurity and the second conductive layer including the first-type impurity, and is positioned in a peripheral region. 
     
     
         9 . The method of  claim 8 , further comprising forming a first contact plug connected to the second conductive layer of the pipe gate and a second contact plug connected to the second conductive layer of the gate electrode. 
     
     
         10 . The method of  claim 8 , further comprising forming a first contact plug connected to the second region of the first conductive layer of the pipe gate and a second contact plug connected to the first conductive layer of the gate electrode.