Semiconductor device

Abstract

The instant disclosure relates to a semiconductor device includes a semiconductor substrate, a plurality of buried bit lines, a plurality of insulating structures, and a plurality of self-aligned spacers. The semiconductor substrate has a plurality of active areas defined thereon. The buried bit lines are disposed in the semiconductor substrate, wherein two of the buried bit lines are positioned in each of the active areas. The insulating structures are disposed on the semiconductor substrate, wherein each of the insulating structures is positioned on and opposite to the two of the buried bit lines. The self-aligned spacers are disposed on the sidewalls of the insulating structures respectively to partially expose the surface of the semiconductor substrate.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor substrate defined a plurality of active areas thereon;   a plurality of buried bit lines disposed in the semiconductor substrate, wherein at least two of the buried bit lines are positioned in each of the active areas;   a plurality of insulating structures disposed on the semiconductor substrate, wherein each of the insulating structures is positioned on and opposite to the at least two of the buried bit lines; and   a plurality of self-aligned spacers disposed on the sidewalls of the insulating structures respectively to partially expose the surface of the semiconductor substrate.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the semiconductor substrate includes a substrate, a pad layer disposed on the substrate, a first mask layer disposed on the pad layer, and a second mask layer disposed on the first mask layer. 
     
     
         3 . The semiconductor device according to  claim 2 , wherein the pad layer is made from oxide or nitride. 
     
     
         4 . The semiconductor device according to  claim 2 , wherein the first mask layer is made from silicon nitride, silicon oxide, or polysilicon, and the second mask layer is made from silicon nitride, silicon oxide, or polysilicon. 
     
     
         5 . The semiconductor device according to  claim 2 , wherein the semiconductor substrate has a plurality self-aligned isolation trenches that pass through the second mask layer, the first mask layer, and the pad layer by a dry-etch process with the self-aligned spacers as masks. 
     
     
         6 . The semiconductor device according to  claim 1 , wherein each of the self-aligned spacers with a predetermined width is configured to define a vertically overlapped capacitor landing area, and the at least two of the buried bit lines in every active area are configured to define a vertically overlapped bit line contact area therebetween. 
     
     
         7 . The semiconductor device according to  claim 5 , wherein each of the capacitor landing areas has a width equal to the maximum width of the corresponding self-aligned spacer. 
     
     
         8 . The semiconductor device according to  claim 1 , wherein each of the self-aligned spacers is made from silicon oxide, silicon nitride, or silicon carbide.