Stress enhanced high voltage device

Abstract

A method of forming a device is disclosed. A substrate having a device region is provided. The device region comprises a source region, a gate region and a drain region defined thereon. A gate is formed in the gate region, a source is formed in the source region and drain is formed in the drain region. A trench is formed in an isolation region in the device region. The isolation region underlaps a portion of the gate. An etch stop (ES) stressor layer is formed over the substrate. The ES stressor layer lines the trench.

What is claimed is:  
     
         1 . A semiconductor device comprising:
 a substrate having a device region surrounded by a device isolation region, wherein the device region comprises a source region, a gate region and a drain region defined thereon;   a transistor which comprises agate in the gate region, a source in the source region and a drain in the drain region;   an internal isolation region which comprises isolation material, wherein the internal isolation region displaces the drain from a drain side of the gate and underlaps a portion of the gate on the drain side of the gate;   a first second trench disposed in the internal isolation region, wherein a width of the first secondary trench is smaller than a width of the internal isolation region;   an etch stop (ES) stressor layer disposed over the substrate, wherein the ES stressor layer lines the transistor and first secondary trench without filling the first secondary trench; and   a dielectric layer disposed on the ES stressor layer over the substrate, wherein the dielectric layer covers the transistor and fills the first secondary trench.   
     
     
         2 . The semiconductor device of  claim 1  wherein the internal isolation region is disposed along a channel width direction in the substrate between the gate and drain. 
     
     
         3 . The semiconductor device of  claim 1  comprising a drift well in the substrate between the gate and drain region, wherein the drift well underlaps a portion of the gate. 
     
     
         4 . The semiconductor device of  claim 3  wherein the drift well encompasses the drain and internal isolation region. 
     
     
         5 . The semiconductor device of  claim 1  wherein the device isolation region isolates the device region from other regions of the device. 
     
     
         6 . The semiconductor device of  claim 5  comprising a device well and a drift well disposed within the device isolation region. 
     
     
         7 . The semiconductor device of  claim 6  wherein the device well encompasses the source, drain, drift well and internal isolation region. 
     
     
         8 . The semiconductor device of  claim 1  wherein:
 the first secondary trench extends to about 90-100% of the depth of the internal isolation region; and 
 the ES stressor layer induces a first stress on a channel and a drift well of the device. 
 
     
     
         9 . The semiconductor device of claim I wherein the ES stressor layer comprises dielectric material. 
     
     
         10 . The semiconductor device of  claim 9  wherein the ES stressor layer comprises silicon nitride. 
     
     
         11 . The semiconductor device of  claim 1  wherein the ES stressor layer induces a first stress on a channel and a drift well of the device. 
     
     
         12 . The semiconductor device of  claim 11  wherein the device is a NMOS transistor, and wherein the first stress is a tensile stress. 
     
     
         13 . The semiconductor device of  claim 11  wherein the device is a PMOS transistor, and wherein the first stress is a compressive stress. 
     
     
         14 . The semiconductor device of  claim 1  wherein:
 the source is adjacent to a source side of the gate; 
 the isolation material of the internal isolation region comprises a dielectric material; and 
 at least sidewalls of the first secondary trench are surrounded by isolation material of the internal isolation region. 
 
     
     
         15 . A semiconductor device comprising:
 a substrate having a device region surrounded by a device isolation region, the device region comprises an internal isolation region, wherein
 the device and internal isolation regions comprise isolation material, and 
 the device region comprises a source region, a gate region and a drain region defined thereon; 
   a gate in the gate region, a source in the source region and a drain in the drain region, the source and drain are disposed within the substrate and below the gate, wherein the drain is separated from a second side of the gate by the internal isolation region and the source is adjacent to a first side of the gate;   a first secondary trench disposed in the isolation material of the internal isolation region and a second. secondary trench disposed in the isolation material of the device isolation region which is adjacent to and contacts the drain; and   an etch stop (ES) stressor layer disposed over the substrate, wherein the ES stressor layer lines the first and second secondary trenches without filling the trenches.   
     
     
         16 . The semiconductor device of  claim 15  comprising a drift well in the substrate between the gate and drain regions, wherein the drift well underlaps a portion of the gate. 
     
     
         17 . The semiconductor device of  claim 15  wherein the ES stressor layer induces a first stress on a channel and a drift well of the device. 
     
     
         18 . The semiconductor device of  claim 17  wherein the device is a NMOS transistor, and wherein the first stress is a tensile stress. 
     
     
         19 . The semiconductor device of  claim 17  wherein the device is a PMOS transistor, and wherein the first stress is a compressive stress. 
     
     
         20 . A semiconductor device comprising:
 a substrate having a device region surrounded by a device isolation region, the device region comprises a gate and first and second heavily doped regions, wherein the first and second heavily doped regions are disposed within the substrate adjacent to first and second sides of the gate;   an internal isolation region which comprises isolation material, wherein the internal isolation region displaces the second heavily doped region from the second side of the gate;   a first secondary trench disposed in at least the internal isolation region, wherein a width of the first secondary trench is smaller than a width of the internal isolation region; and   an etch stop (ES) stressor layer disposed over the substrate, wherein the ES stressor layer lines the first secondary trench without filling the first secondary trench.