Multi-height fin field effect transistors

Abstract

Semiconductor fins are formed on a top surface of a substrate. A dielectric material is deposited on the top surfaces of the semiconductor fins and the substrate by an anisotropic deposition. A dielectric material layer on the top surface of the substrate is patterned so that the remaining portion of the dielectric material layer laterally surrounds each bottom portion of at least one semiconductor fin, while not contacting at least one second semiconductor fin. Dielectric material portions on the top surfaces of the semiconductor fins may be optionally removed. Each first semiconductor fin has a lesser channel height than the at least one second semiconductor fin. The first and second semiconductor fins can be employed to provide fin field effect transistors having different channel heights.

1 . A semiconductor structure comprising:
 a first semiconductor fin and a second semiconductor fin that are located on a substrate;   a dielectric material layer located on said substrate and contacting, and laterally surrounding, a lower portion of said first semiconductor fin; and   at least one gate dielectric including a first gate dielectric portion straddling said first semiconductor fin and a second gate dielectric portion straddling said second semiconductor fin, wherein said first gate dielectric portion contacts a top surface of said dielectric material layer and sidewalls of said first semiconductor fin, and said second gate dielectric portion contacts a top surface of said substrate and sidewalls of said second semiconductor fin.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein top surfaces of said first semiconductor fin and said second semiconductor fin are coplanar. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein bottom surfaces of said first semiconductor fin and said second semiconductor fin are coplanar. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein an interface between said first semiconductor fin and said first gate dielectric portion extends from said top surface of said dielectric material layer to a top surface of said first semiconductor fin. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein an interface between said second semiconductor fin and said second gate dielectric portion extends from said top surface of said substrate to a top surface of said second semiconductor fin. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein said first semiconductor fin and said second semiconductor fin have a height from 20 nm to 300 nm. 
     
     
         7 . The semiconductor structure of  claim 1 , further comprising a dielectric material portion contacting a top surface of said first semiconductor fin, wherein said second gate dielectric portion contacts a top surface of said second semiconductor fin. 
     
     
         8 . The semiconductor structure of  claim 7 , wherein said dielectric material portion and said dielectric material layer have a same composition and a same thickness. 
     
     
         9 . The semiconductor structure of  claim 7 , further comprising a raised active region comprising a doped semiconductor material, contacting sidewalls of said dielectric material portion, and epitaxially aligned to a single crystalline semiconductor material within said first semiconductor fin. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein said first gate dielectric portion contacts a top surface of said first semiconductor fin, and said second gate dielectric portion contacts a top surface of said second semiconductor fin. 
     
     
         11 . The semiconductor structure of  claim 1 , further comprising a gate electrode that contiguously extends over said first gate dielectric portion and said second gate dielectric portion. 
     
     
         12 . The semiconductor structure of  claim 1 , further comprising an insulator material layer contacting a surface of said first semiconductor fin and a surface of said second semiconductor fin, wherein a bottom surface of said first gate dielectric portion is spaced from said insulator material layer by said dielectric material layer, and a bottom surface of said second gate dielectric portion contacts a top surface of said insulator material layer. 
     
     
         13 .- 20 . (canceled) 
     
     
         21 . The semiconductor structure of  claim 1 , wherein said substrate comprises a buried insulator layer and a handle substrate. 
     
     
         22 . The semiconductor structure of  claim 1 , wherein said first semiconductor fin and said second semiconductor fin are comprised of the same semiconductor material. 
     
     
         23 . The semiconductor structure of  claim 22 , wherein said semiconductor material comprises single crystalline silicon or a single crystalline alloy of silicon. 
     
     
         24 . The semiconductor structure of  claim 1 , wherein said first semiconductor fin and said second semiconductor fin are comprised of different semiconductor materials. 
     
     
         25 . The semiconductor structure of  claim 1 , further comprising at least one gate structure, wherein said at least one gate structure comprises a vertical stack, from bottom to top, of a gate dielectric, a gate electrode, and a gate cap dielectric. 
     
     
         26 . The semiconductor structure of  claim 25 , wherein said at least one gate structure is in direct contact with a topmost surface of said dielectric material layer. 
     
     
         27 . The semiconductor structure of  claim 25 , further comprising a gate spacer on an outer sidewall of said at least one gate structure. 
     
     
         28 . The semiconductor structure of  claim 27 , wherein said gate spacer is recessed below a topmost surface of said at least one gate structure.