Semiconductor storage device

Abstract

A semiconductor integrated circuit device, includes a first and a second bus line making a bus line pair, and a plurality of circuit units, each of the circuit units including, a first transistor, a second transistor, and a third and a fourth transistor sharing a source or a drain. The circuit units includes a first and a second circuit unit arranged in a first direction. One of a source and a drain of the first transistor of the first circuit unit and one of a source and a drain of the second transistor of the first circuit unit are coupled to the first bus line. The source or the drain shared by the third and the fourth transistor of the first circuit unit is coupled to the second bus line.

What is claimed is: 
     
         1 . A semiconductor integrated circuit device, comprising:
 a first and a second bus line making a bus line pair; and   a plurality of circuit units, each of the circuit units including:
 a first transistor; 
 a second transistor; and 
 a third and a fourth transistor sharing a source or a drain, 
   wherein the circuit units includes a first and a second circuit unit arranged in a first direction,   wherein one of a source and a drain of the first transistor of the first circuit unit and one of a source and a drain of the second transistor of the first circuit unit are coupled to the first bus line,   wherein the source or the drain shared by the third and the fourth transistor of the first circuit unit is coupled to the second bus line,   wherein one of a source and a drain of the first transistor of the second circuit unit and one of a source and a drain of the second transistor of the second circuit unit are coupled to the second bus line, and   wherein the source or the drain shared by the third and the fourth transistor of the second circuit unit is coupled to the first bus line.   
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 , wherein the first, the third, the fourth and the second transistor are arranged in this order in the first direction. 
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 , wherein a gate of the first transistor is coupled to a gate of the third transistor, and a gate of the second transistor is coupled to a gate of the fourth transistor. 
     
     
         4 . The semiconductor integrated circuit device according to  claim 1 , wherein each of the circuit units further comprises fifth to eighth transistors,
 wherein one of a source and a drain of the fifth transistor is shared with the one of the source and the drain of the first transistor,   wherein one of a source and a drain of the sixth transistor is shared with the one of a source and a drain of the second transistor, and   wherein the seventh and the eighth transistor sharing a source or a drain, the source or the drain shared by the seventh and the eighth transistor is shared with the source or the drain shared by the third and the fourth transistor.   
     
     
         5 . The semiconductor integrated circuit device according to  claim 1 , further comprises a first bit line pair and a second bit line pair,
 wherein one of the first bit line pair is coupled to the other of the source and the drain of the first transistor, the other of the first bit line pair is coupled to the other of the source and the drain of the third transistor, and   wherein one of the second bit line pair is coupled to the other of the source and the drain of the second transistor, the other of the second bit line pair is coupled to the other of the source and the drain of the fourth transistor.   
     
     
         6 . The semiconductor integrated circuit device according to  claim 5 , further comprises a plurality of memory cell arrays including a plurality of memory cells,
 wherein the memory cell arrays and the circuit units are alternately arranged in the first direction, and   wherein the memory cells coupled to the one of the first bit line pair and the memory cells coupled to the other of the first bit line pair are arranged in respectively different memory cell arrays.   
     
     
         7 . The semiconductor integrated circuit device according to  claim 5 , further comprises a plurality of memory cell arrays including a plurality of memory cells,
 wherein the memory cell arrays and the circuit units are alternately arranged in the first direction, and   wherein the memory cells coupled to the one of the first bit line pair and the memory cells coupled to the other of the first bit line pair are arranged in the same memory cell array.   
     
     
         8 . A semiconductor integrated circuit device, comprising:
 a first and a second bus line making a bus line pair; and   a plurality of circuit units, each of the circuit units including:
 a first transistor having a first diffusion region as one of a source and a drain, 
 a second transistor having a second diffusion region as one of a source and a drain, and 
 a third and a fourth transistor sharing a third diffusion region as a common source or a common drain, and 
   wherein the first, the second, the third and the fourth transistor are arranged in a first direction,   wherein the circuit units includes a first and a second circuit unit arranged in the first direction,   wherein the first diffusion region of the first circuit unit and the second diffusion region of the first circuit unit are coupled to the first bus line,   wherein the third diffusion region of the first circuit unit is coupled to the second bus line,   wherein the first diffusion region of the second circuit unit and the second diffusion region of the second circuit unit are coupled to the second bus line, and   wherein the third diffusion region of the second circuit unit is coupled to the first bus line.   
     
     
         9 . The semiconductor integrated circuit device according to  claim 8 , wherein each of the circuit units further comprises fifth to eighth transistors,
 wherein the fifth transistor shares the first diffusion region with the first transistor,   wherein the sixth transistor shares with the second diffusion region with the second transistor, and   wherein the seventh and the eighth transistor shares the third diffusion region with the third and the fourth transistor.