US2015280571A1PendingUtilityA1

Power conversion circuit, multiphase voltage regulator, and power conversion method

Assignee: RENESAS ELECTRONICS CORPPriority: Sep 22, 2011Filed: Jun 17, 2015Published: Oct 1, 2015
Est. expirySep 22, 2031(~5.1 yrs left)· nominal 20-yr term from priority
H02M 3/158H02M 3/1588Y02B70/10H02M 1/38
49
PatentIndex Score
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Claims

Abstract

Disclosed is a power conversion circuit that suppresses the flow of a through current to a switching element based on a normally-on transistor. The power conversion circuit includes a high-side transistor and a low-side transistor, which are series-coupled to each other to form a half-bridge circuit, and two drive circuits, which complementarily drive the gate of the high-side transistor and of the low-side transistor. The high-side transistor is a normally-off transistor. The low-side transistor is a normally-on transistor.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device including a power conversion circuit, comprising:
 a high-side transistor;   a low-side transistor,
 the high-side transistor and the low-side transistor being coupled in series to form a half-bridge circuit of the power conversion circuit; 
   a first drive circuit configured to drive the high-side transistor;   a second drive circuit configured to drive the low-side transistor;   a driver control circuit configured to control the first drive circuit and the second drive circuit; and   a resin sealing the high-side transistor, the low-side transistor, the first drive circuit, the second drive circuit and the driver control circuit,   wherein each of the high-side transistor and the low-side transistor includes an electron transit layer containing gallium nitride,   wherein the high-side transistor is a normally-off transistor, and   wherein the low-side transistor is a normally-on transistor.   
     
     
         2 . The power conversion circuit according to  claim 1 ,
 wherein the first drive circuit controls switching of the high-side transistor in accordance with an input pulse width modulation (PWM) signal when a first power supply voltage for the second drive circuit is lower than a first reference voltage, and the first drive circuit turns off the high-side transistor when the first power supply voltage for the second drive circuit is higher than the first reference voltage, and   wherein the second drive circuit outputs a drive signal to the low-side transistor in accordance with the first power supply voltage, which is supplied as a low-potential power supply voltage.   
     
     
         3 . The power conversion circuit according to  claim 2 , further comprising:
 a negative voltage source that generates the first power supply voltage in accordance with a second power supply voltage and a ground voltage.   
     
     
         4 . The power conversion circuit according to  claim 2 , wherein the driver control circuit outputs a first logic level when the first power supply voltage is lower than the first reference voltage, and outputs a second logic level when the first power supply voltage is higher than the first reference voltage, and
 wherein the first drive circuit supplies a drive signal to the high-side transistor in accordance with the second logic level, which is output from the control circuit, and turns off the high-side transistor.   
     
     
         5 . The power conversion circuit according to  claim 2 , wherein the first drive circuit outputs a drive signal to the high-side transistor in accordance with a second power supply voltage for the first drive circuit, which is supplied as a high-potential power supply voltage, and
 wherein the first drive circuit turns off the high-side transistor when the second power supply voltage is lower than a second reference voltage.   
     
     
         6 . The power conversion circuit according to  claim 5 , wherein the driver control circuit outputs a first logic level when the second power supply voltage is higher than the second reference voltage, and outputs a second logic level when the first power supply voltage is higher than the second reference voltage, and
 wherein the first drive circuit supplies a drive signal to the high-side transistor in accordance with the second logic level, which is output from the driver control circuit, and turns off the high-side transistor.   
     
     
         7 . The power conversion circuit according to  claim 2 , wherein the second drive circuit controls the switching operation of the low-side transistor in accordance with the input PWM signal when a second power supply voltage for the first drive circuit is higher than a second reference voltage, and the second drive circuit turns off the low-side transistor when the second power supply voltage is lower than the second reference voltage. 
     
     
         8 . The power conversion circuit according to  claim 7 , wherein the second drive circuit outputs a drive signal to the low-side transistor in accordance with the first power supply voltage, and
 wherein the second drive circuit turns off the low-side transistor when the first power supply voltage is higher than the first reference voltage.   
     
     
         9 . The power conversion circuit according to  claim 8 , wherein the driver control circuit outputs a first logic level when the first power supply voltage is lower than the first reference voltage, and outputs a second logic level when the first power supply voltage is higher than the first reference voltage,
 wherein the first drive circuit supplies a drive signal to the high-side transistor in accordance with the second logic level, which is output from the control circuit, and turns off the high-side transistor, and   wherein the second drive circuit supplies a drive signal to the low-side transistor in accordance with the second logic level, which is output from the control circuit, and turns off the low-side transistor.   
     
     
         10 . The power conversion circuit according to  claim 7 , wherein the first drive circuit outputs a drive signal to the high-side transistor in accordance with the second power supply voltage supplied as a high-potential power supply voltage, and
 wherein, when the second power supply voltage is lower than the second reference voltage, the first drive circuit turns off the high-side transistor, and   wherein the second drive circuit turns off the low-side transistor when the second power supply voltage is lower than the second reference voltage.   
     
     
         11 . The power conversion circuit according to  claim 10 , wherein the driver control circuit outputs a first logic level when the second power supply voltage is higher than the second reference voltage, and outputs a second logic level when the first power supply voltage is higher than the second reference voltage,
 wherein the first drive circuit supplies a drive signal to the high-side transistor in accordance with the second logic level, which is output from the control circuit, and turns off the high-side transistor, and   wherein the second drive circuit supplies a drive signal to the low-side transistor in accordance with the second logic level, which is output from the control circuit, and turns off the low-side transistor.   
     
     
         12 . The power conversion circuit according to  claim 1 , wherein the high-side transistor includes:
 a substrate;   the electron transit layer disposed over the substrate;   an electron supply layer containing aluminum gallium nitride disposed over the electron transit layer;   a gate electrode disposed in a recess in the electron supply layer;   a source electrode disposed over the electron transit layer; and   a drain electrode disposed over the electron transit layer.   
     
     
         13 . The power conversion circuit according to  claim 12 , wherein, in the high-side transistor, the electron supply layer has a greater band gap energy than the electron transit layer. 
     
     
         14 . The power conversion circuit according to  claim 1 , wherein the low-side transistor includes:
 a substrate;   the electron transit layer disposed over the substrate;   an electron supply layer containing aluminum gallium nitride disposed over the electron transit layer;   a gate electrode disposed over the electron supply layer;   a source electrode disposed over the electron transit layer; and   a drain electrode disposed over the electron transit layer.   
     
     
         15 . The power conversion circuit according to  claim 14 , wherein the high-side transistor includes:
 the substrate;   the electron transit layer disposed over the substrate;   an electron supply layer containing aluminum gallium nitride disposed over the electron transit layer;   a gate electrode disposed in a recess in the electron supply layer;   a source electrode disposed over the electron transit layer; and   a drain electrode disposed over the electron transit layer.   
     
     
         16 . The power conversion circuit according to  claim 15 , wherein, in the low-side transistor, the electron supply layer has a greater band gap energy than the electron transit layer. 
     
     
         17 . The power conversion circuit according to  claim 16 , wherein, in the high-side transistor, the electron supply layer has a greater band gap energy than the electron transit layer. 
     
     
         18 . The power conversion circuit according to  claim 14 , wherein, in the low-side transistor, the electron supply layer has a greater band gap energy than the electron transit layer. 
     
     
         19 . The power conversion circuit according to  claim 15 , wherein, in the low-side transistor, the electron supply layer extends between the source electrode and the drain electrode. 
     
     
         20 . The power conversion circuit according to  claim 15 , wherein in the high-side transistor, a gate insulation film is disposed in the recess between the gate electrode and the electron transit layer, and
 wherein in the low-side transistor, a gate insulation film is disposed between the gate electrode and the electron transit layer.

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