Finfet devices with different fin heights in the channel and source/drain regions

Abstract

One method disclosed includes, forming a sacrificial gate structure trench in a stack of sacrificial material layers, forming a sacrificial gate structure within the trench, performing at least one process operation to remove at least portions of the stack of sacrificial material layers and thereby expose sidewalls of the sacrificial gate structure, forming a sidewall spacer adjacent the exposed sidewalls of the sacrificial gate structure, removing the sacrificial gate structure so as to define a replacement gate cavity between the spacers, forming a replacement gate structure in the replacement gate cavity, and forming a gate cap above the replacement gate structure within the replacement gate cavity.

1 - 15 . (canceled) 
     
     
         16 . A FinFET transistor device comprising a channel region and a plurality of source/drain regions, comprising:
 a fin defined by a plurality of trenches in a semiconductor substrate;   a gate structure positioned around said fin; and   a layer of insulating material positioned in said trenches, wherein a first portion of said layer of insulating material positioned under said gate structure has a first thickness and a second portion of said layer of insulating material positioned below said source/drain regions has a second thickness, said first thickness being less than said second thickness.   
     
     
         17 . The device of  claim 16 , wherein said fin has a first exposed height in said source/drain regions and a second exposed height under said gate structure, said second height being greater than said first height. 
     
     
         18 . The device of  claim 16 , wherein said gate structure has an inwardly tapered cross-sectional profile in a gate length direction of said device, said gate structure having an upper surface that is wider than a lower surface of said gate structure that is positioned proximate an upper surface of said substrate. 
     
     
         19 . The device of  claim 16 , wherein said gate structure has inwardly-tapered sidewalls that are tapered at an angle that falls within a range of 1-5° relative to a line normal to an upper surface of said substrate. 
     
     
         20 . A FinFET transistor device comprising a channel region and a plurality of source/drain regions, comprising:
 a fin defined by a plurality of trenches in a semiconductor substrate;   a gate structure positioned around said fin, wherein said fin has a first exposed height in said source/drain regions and a second exposed height under said gate structure, said second height being greater than said first height; and   a layer of insulating material positioned in said trenches, wherein a first portion of said layer of insulating material positioned under said gate structure has a first thickness and a second portion of said layer of insulating material positioned below said source/drain regions has a second thickness, said first thickness being less than said second thickness, wherein an upper surface of said first portion of said layer of insulating material defines said first exposed height of said fin and an upper surface of said second portion of said layer of insulating material defines said second exposed height of said fin.   
     
     
         21 . The device of  claim 20 , wherein said gate structure has an inwardly tapered cross-sectional profile in a gate length direction of said device, said gate structure having an upper surface that is wider than a lower surface of said gate structure that is positioned proximate an upper surface of said substrate. 
     
     
         22 . The device of  claim 21 , wherein said gate structure has inwardly-tapered sidewalls that are tapered at an angle that falls within a range of 1-5° relative to a line normal to an upper surface of said substrate. 
     
     
         23 . A FinFET transistor device comprising a channel region and a plurality of source/drain regions, comprising:
 a fin defined by a plurality of trenches in a semiconductor substrate;   a gate structure positioned around said fin, wherein said fin has a first exposed height in said source/drain regions and a second exposed height under said gate structure, said second height being greater than said first height; and   a layer of insulating material having a non-uniform thickness positioned in said trenches.   
     
     
         24 . The device of  claim 23 , wherein said gate structure has an inwardly tapered cross-sectional profile in a gate length direction of said device, said gate structure having an upper surface that is wider than a lower surface of said gate structure that is positioned proximate an upper surface of said substrate. 
     
     
         25 . The device of  claim 24 , wherein said gate structure has inwardly-tapered sidewalls that are tapered at an angle that falls within a range of 1-5° relative to a line normal to an upper surface of said substrate. 
     
     
         26 . The device of  claim 23 , wherein a first portion of said non-uniform thickness layer of insulating material positioned under said gate structure has an upper surface that defines said first exposed height of said fin and a second portion of said non-uniform thickness layer of insulating material positioned below said source/drain regions has an upper surface that defines said second exposed height of said fin. 
     
     
         27 . The device of  claim 26 , wherein said first portion of said non-uniform thickness layer of insulating material is thicker than said second portion of said non-uniform thickness layer of insulating material.