Structure and method to obtain eot scaled dielectric stacks

Abstract

Equivalent oxide thickness (EOT) scaled high k/metal gate stacks are provided in which the capacitance bottleneck of the interfacial layer is substantially eliminated, with minimal compromise on the mobility of carriers in the channel of the device. In one embodiment, the aforementioned EOT scaled high k/metal gate stacks are achieved by increasing the dielectric constant of the interfacial layer to a value that is greater than the originally formed interfacial layer, i.e., the interfacial layer prior to diffusion of a high k material dopant element therein. In another embodiment, the aforementioned scaled high k/metal gate stacks are achieved by eliminating the interfacial layer from the structure. In yet another embodiment, the aforementioned high k/metal gate stacks are achieved by both increasing the dielectric constant of the interfacial layer and reducing/eliminating the interfacial layer.

What is claimed is: 
     
         1 . A method of forming a semiconductor structure comprising:
 providing a semiconductor substrate having an nFET device region and a pFET device region; and   providing an EOT scaled nFET in said nFET device region and an EOT scaled pFET in said pFET device region, said EOT scaled nFET including, from bottom to top, an nFET modified interfacial layer including an nFET threshold voltage adjusting element incorporated therein, a first high k gate dielectric portion, a first metallic electrode portion and a first Si-containing electrode portion, and said EOT scaled pFET including, from bottom to top, a pFET modified interfacial layer including a pFET threshold voltage adjusting element incorporated therein, a second high k gate dielectric portion, a second metallic electrode portion and a second Si-containing electrode portion.   
     
     
         2 . The method of  claim 1 , wherein said nFET modified interfacial layer comprises a reaction product of a semiconductor material and said nFET threshold voltage adjusting element. 
     
     
         3 . The method of  claim 2 , wherein said semiconductor material comprises a semiconductor oxide, a semiconductor nitride or a nitrided semiconductor oxide. 
     
     
         4 . The method of  claim 1 , wherein said pFET modified interfacial layer comprises a reaction product of a semiconductor material and said pFET threshold voltage adjusting element. 
     
     
         5 . The method of  claim 4 , wherein said semiconductor material comprises a semiconductor oxide, a semiconductor nitride or a nitrided semiconductor oxide. 
     
     
         6 . The method of  claim 2 , wherein said nFET threshold voltage adjusting element is a rare earth metal. 
     
     
         7 . The method of  claim 2 , wherein said nFET threshold adjusting voltage element is an alkaline earth metal. 
     
     
         8 . The method of  claim 4 , wherein said pFET threshold voltage adjusting element comprises Al, Ge, Ti, Ni, Co, Tl or Ta. 
     
     
         9 . The method of  claim 1 , wherein said providing said EOT scaled nFET and said EOT scaled pFET comprises:
 forming an interfacial layer within said nFET device region and said pFET device region;   forming a high k gate dielectric layer atop said interfacial layer;   forming a patterned nFET threshold voltage adjusting material atop said high k dielectric layer in said nFET device region and a patterned pFET threshold adjusting material atop said high k dielectric layer in said pFET device region;   forming a metallic electrode layer atop said patterned nFET threshold voltage adjusting material and atop said patterned pFET threshold voltage adjusting material;   forming a Si-containing electrode layer atop said metallic electrode layer, wherein during said forming said metallic electrode layer or forming said Si-containing electrode layer metallic species from said patterned nFET threshold voltage adjusting material and said patterned pFET threshold voltage adjusting material diffuse into said interfacial layer forming said nFET modified interfacial layer and said pFET modified interfacial layer; and   patterning at least said Si-containing layer, said metallic electrode layer, said high gate dielectric layer to provide said EOT scaled nFET and said EOT scaled pFET.   
     
     
         10 . The method of  claim 9 , wherein at least one of said patterned nFET voltage adjusting material and said patterned nFET voltage adjusting material is completely consumed after said diffusion of said metallic element from said nFET threshold voltage adjusting material and said pFET threshold voltage adjusting material. 
     
     
         11 . The method of  claim 9 , wherein at least one of said patterned nFET voltage adjusting material and said patterned nFET voltage adjusting material is partially consumed after said diffusion of metallic element from said nFET threshold voltage adjusting material and said pFET threshold voltage adjusting material. 
     
     
         12 . The method of  claim 1 , wherein said providing said EOT scaled nFET and said EOT scaled pFET comprises:
 forming an interfacial layer in said nFET device region and said pFET device region;   forming a high k gate dielectric layer atop said interfacial layer;   forming a patterned nFET threshold voltage adjusting material atop said high k dielectric layer in said nFET device region and a patterned pFET threshold adjusting material atop said high k dielectric layer in said pFET device region;   annealing to cause diffusion of metallic species from said patterned nFET threshold voltage adjusting material and said patterned pFET threshold voltage adjusting material into said interfacial layer forming said nFET modified interfacial layer and said pFET modified interfacial layer;   forming a metallic electrode layer in both said nFET device region and said pFET device region;   forming a Si-containing electrode layer atop said metallic electrode layer; and   patterning at least said Si-containing layer, said metallic electrode layer, said high gate dielectric layer to provide said EOT scaled nFET and said EOT scaled pFET.   
     
     
         13 . The method of  claim 1 , wherein said providing said EOT scaled nFET and said EOT scaled pFET comprises:
 forming an interfacial layer in said nFET device region and said pFET device region;   forming a high k gate dielectric layer atop said interfacial layer;   forming a patterned nFET threshold voltage adjusting material atop said high k dielectric layer in said nFET device region and a patterned pFET threshold adjusting material atop said high k dielectric layer in said pFET device region;   forming a metallic electrode layer atop said patterned nFET threshold voltage adjusting material and atop said patterned pFET threshold voltage adjusting material;   annealing to cause diffusion of metallic species from said patterned nFET threshold voltage adjusting material and said patterned pFET threshold voltage adjusting material into said interfacial layer forming said nFET modified interfacial layer and said pFET modified interfacial layer;   forming a Si-containing electrode layer atop said metallic electrode layer; and   patterning at least said Si-containing layer, said metallic electrode layer, said high gate dielectric layer to provide said EOT scaled nFET and said EOT scaled pFET.   
     
     
         14 . The method of  claim 1 , wherein said providing said EOT scaled nFET and said EOT scaled pFET comprises:
 forming an interfacial layer in said nFET device region and said pFET device region;   forming a high k gate dielectric layer atop said interfacial layer;   forming a patterned nFET threshold voltage adjusting material atop said high k dielectric layer in said nFET device region and a patterned pFET threshold adjusting material atop said high k dielectric layer in said pFET device region;   forming a metallic electrode layer atop said patterned nFET threshold voltage adjusting material and atop said patterned pFET threshold voltage adjusting material;   forming a Si-containing electrode layer atop said metallic electrode layer;   annealing to cause diffusion of metallic species from said patterned nFET threshold voltage adjusting material and said patterned pFET threshold voltage adjusting material into said interfacial layer forming said nFET modified interfacial layer and said pFET modified interfacial layer; and   patterning at least said Si-containing layer, said metallic electrode layer, said high gate dielectric layer to provide said EOT scaled nFET and said EOT scaled pFET.   
     
     
         15 . The method of  claim 1 , wherein said providing said EOT scaled nFET and said EOT scaled pFET comprises:
 forming an interfacial layer in said nFET device region and said pFET device region;   forming a patterned nFET threshold voltage adjusting material atop said interfacial layer in said nFET device region and a patterned pFET threshold adjusting material atop said interfacial layer in said pFET device region;   forming a high k gate dielectric layer atop said patterned pFET threshold adjusting material and said nFET threshold voltage material;   forming a metallic electrode layer atop said high gate dielectric layer   forming a Si-containing electrode layer atop said metallic electrode layer; and   patterning at least said Si-containing layer, said metallic electrode layer, said high gate dielectric layer to provide said EOT scaled nFET and said EOT scaled pFET,   wherein after forming said patterned nFET threshold voltage adjusting material and said patterned pFET threshold adjusting material metallic species from said patterned nFET threshold voltage adjusting material and said patterned pFET threshold voltage adjusting material are diffused into said interfacial layer forming said nFET modified interfacial layer and said pFET modified interfacial layer.   
     
     
         16 . The method of  claim 1 , wherein said providing said EOT scaled nFET and said EOT scaled pFET comprises:
 forming an interfacial layer within said nFET device region and said pFET device region;   forming a high k gate dielectric layer atop interfacial layer;   forming a metallic electrode layer atop said high gate dielectric layer, wherein said metallic electrode layer includes a first portion located atop said nFET device region that includes an nFET threshold adjusting material and a second portion located atop said pFET device region that includes an pFET threshold adjusting material;   forming a Si-containing electrode layer atop said metallic electrode layer; and   patterning at least said Si-containing layer, said metallic electrode layer, said high gate dielectric layer to provide said EOT scaled nFET and said EOT scaled pFET,   wherein after forming said metallic electrode layer species from said first portion and said second portion of said metallic electrode layer are diffused into said interfacial layer forming said nFET modified interfacial layer and said pFET modified interfacial layer.