Method and apparatus for reducing power usage during video presentation on a display

Abstract

An apparatus may include a link component and a display component. The link component may be operative to receive media content via data frames over a display interconnect, the data frames received periodically in succession at a first rate corresponding to a native frame rate of the media content. The display component may be operative to display the data frames in succession at a second rate corresponding to a native refresh rate of the display component, the display component operative to re-display data frames already shown to maintain the second rate when new data frames have not been received over the display interconnect.

1 - 38 . (canceled) 
     
     
         39 . An apparatus, comprising:
 a processor;   a display engine operative to:
 receive a set of video data of a digital medium; 
 render the set of video data to generate multiple video data frames; 
 send the multiple video data frames over a display interconnect, the multiple video data frames sent periodically in succession at a first rate corresponding to a native frame rate of the digital medium; and 
 send a request to confirm a capability for low-power video transfer and to receive a response indicating the capability for low-power video transfer. 
   
     
     
         40 . The apparatus of  claim 39 , the display engine operative to send a control signal to place the processor into a low power state during a period when the multiple video data frames are sent over the display interconnect. 
     
     
         41 . The apparatus of  claim 40 , the display engine operative to set a timer to generate a control signal to wake the processor from the low power state. 
     
     
         42 . The apparatus of  claim 41 , the display engine to set the timer based on the number of video data frames of the multiple video data frames and the frame rate of the digital medium. 
     
     
         43 . The apparatus of  claim 42 , the processor comprising a central processing unit or a graphics processing unit. 
     
     
         44 . The apparatus of  claim 43 , comprising a display interface, the control signal to place the processor and the display interface in the low power state. 
     
     
         45 . The apparatus of  claim 44 , comprising a voltage regulator, the control signal to place the processor, the display interface, and the voltage regulator in the low power state. 
     
     
         46 . The apparatus of  claim 39 , the display engine operative to:
 identify a first video data frame currently being sent over the display interconnect; and   interrogate a command queue to identify a video frame corresponding to the first video data frame; and   interrogate the command queue to identify a plurality of second video frames ahead of the first video frame, the set of video data of the digital medium corresponding to the second video frames.   
     
     
         47 . The apparatus of  claim 39 , comprising a memory storage device, the display component to store the multiple video data frames on the non-transient memory storage device. 
     
     
         48 . A computer-implemented method, comprising:
 receiving a set of video data of a digital medium;   rendering the set of video data to generate multiple video data frames;   sending the multiple video data frames over a display interconnect, the multiple video data frames sent periodically in succession at a first rate corresponding to a native frame rate of the digital medium; and   sending a request to confirm a capability for low-power video transfer and to receive a response indicating the capability for low-power video transfer.   
     
     
         49 . The computer-implemented method of  claim 48 , comprising sending a control signal to place a processor into a low power state during a period when the multiple video data frames are sent over the display interconnect. 
     
     
         50 . The computer-implemented method of  claim 49 , comprising setting a timer to generate a control signal to wake the processor from the low power state. 
     
     
         51 . The computer-implemented method of  claim 50 , comprising setting the timer based on the number of video data frames of the multiple video data frames and the frame rate of the digital medium. 
     
     
         52 . The computer-implemented method of  claim 51 , the processor comprising a central processing unit or a graphics processing unit. 
     
     
         53 . The computer-implemented method of  claim 52 , the control signal to place the processor and a display interface in the low power state. 
     
     
         54 . The computer-implemented method of  claim 53 , the control signal to place the processor, the display interface, and a voltage regulator in the low power state. 
     
     
         55 . The computer-implemented method of  claim 48 , comprising:
 identifying a first video data frame currently being sent over the display interconnect; and   interrogating a command queue to identify a video frame corresponding to the first video data frame; and   interrogating the command queue to identify a plurality of second video frames ahead of the first video frame, the set of video data of the digital medium corresponding to the second video frames.   
     
     
         56 . The computer-implemented method of  claim 48 , comprising storing the multiple video data frames on the non-transient memory storage device. 
     
     
         57 . At least one non-transitory computer-readable storage medium comprising a plurality of instructions that in response to being executed on a computing device cause the computing device to:
 receive a set of video data of a digital medium;   render the set of video data to generate multiple video data frames;   send the multiple video data frames over a display interconnect, the multiple video data frames sent periodically in succession at a first rate corresponding to a native frame rate of the digital medium; and   send a request to confirm a capability for low-power video transfer and to receive a response indicating the capability for low-power video transfer.   
     
     
         58 . The at least one non-transitory computer-readable storage medium of  claim 57 , comprising a plurality of instructions that in response to being executed on a computing device cause the computing device to send a control signal to place a processor into a low power state during a period when the multiple video data frames are sent over the display interconnect. 
     
     
         59 . The at least one non-transitory computer-readable storage medium of  claim 58 , comprising a plurality of instructions that in response to being executed on a computing device cause the computing device to set a timer to generate a control signal to wake the processor from the low power state. 
     
     
         60 . The at least one non-transitory computer-readable storage medium of  claim 57 , comprising a plurality of instructions that in response to being executed on a computing device cause the computing device to set the timer based on the number of video data frames of the multiple video data frames and the frame rate of the digital medium. 
     
     
         61 . The at least one non-transitory computer-readable storage medium of  claim 57 , the control signal to place the processor, a display interface, and a voltage regulator in the low power state. 
     
     
         62 . The at least one non-transitory computer-readable storage medium of  claim 57 , comprising a plurality of instructions that in response to being executed on a computing device cause the computing device to:
 identify a first video data frame currently being sent over the display interconnect; and   interrogate a command queue to identify a video frame corresponding to the first video data frame; and   interrogate the command queue to identify a plurality of second video frames ahead of the first video frame, the set of video data of the digital medium corresponding to the second video frames.   
     
     
         63 . The at least one non-transitory computer-readable storage medium of  claim 57 , comprising a plurality of instructions that in response to being executed on a computing device cause the computing device to store the multiple video data frames on the non-transient memory storage device.