Programmable equalization with compensated impedance

Abstract

Described is a chip comprising: a pull-up driver with a first impedance, the pull-up driver coupled to a node; a pull-down driver with a second impedance, the pull-down driver coupled to the node; and an equalizer coupled to the pull-up and pull-down drivers, wherein the equalizer is operable to be trained to deemphasize a signal driven on the node while maintaining the first and second impedances substantially constant.

1 . A chip comprising:
 a pull-up driver with a first impedance, the pull-up driver coupled to a node;   a pull-down driver with a second impedance, the pull-down driver coupled to the node; and   an equalizer coupled to the pull-up and pull-down drivers, wherein the equalizer is operable to be trained to deemphasize a signal driven on the node while maintaining the first and second impedances substantially constant.   
     
     
         2 . The chip of  claim 1 , wherein the equalizer is part of a parallel input-output (I/O) link. 
     
     
         3 . The chip of  claim 1 , wherein the first impedance is independently controllable from control of the second impedance. 
     
     
         4 . The chip of  claim 1  further comprises:
 a pull-up driver compensation unit which is operable to determine a code for setting the first impedance for the pull-up driver, and a code for setting a pull-up granularity for de-emphasizing the signal by the equalizer. 
 
     
     
         5 . The chip of  claim 4  further comprises:
 a pull-down driver compensation unit which is operable to determine a code for setting the second impedance for the pull-down driver, and a code for setting a pull-down granularity for de-emphasizing the signal by the equalizer. 
 
     
     
         6 . The chip of  claim 4 , wherein the equalizer is disabled when the pull-up driver compensation unit is determining the code for setting the first impedance for the pull-up driver. 
     
     
         7 . The chip of  claim 5 , wherein the equalizer is disabled when the pull-down driver compensation unit is determining the code for setting the second impedance for the pull-up driver. 
     
     
         8 . The chip of  claim 5 , wherein the pull-up driver compensation unit and the pull-down driver compensation unit determine the codes for setting the first and second impedances prior to setting the codes for the pull-up and pull-down granularities for de-emphasizing the signal by the equalizer, and wherein the codes, for the pull-up and pull-down granularities for de-emphasizing the signal by the equalizer, are programmable. 
     
     
         9 . The chip of  claim 5 , wherein the pull-up driver compensation unit and the pull-down driver compensation unit are operable to determine codes again for setting the first and second impedances after setting the codes for the pull-up and pull-down granularities for de-emphasizing the signal by the equalizer. 
     
     
         10 . The chip of  claim 5 , wherein the codes for the pull-up and pull-down granularities for de-emphasizing the signal by the equalizer are different when the equalizer is in equalization mode than codes for the pull-up and pull-down granularities when the equalizer is in non-equalization mode. 
     
     
         11 . The chip of  claim 1 , wherein the first and second impedances are substantially constant during a period when the equalizer is in non-equalization mode or equalization mode. 
     
     
         12 . The chip of  claim 1 , wherein the equalizer comprises:
 a pull-up section coupled to the node; and   a pull-down section coupled to the node, wherein the pull-up and pull-down sections are controllable with control signals different from control signals for controlling the first and second impedances of the pull-up and pull-down drivers.   
     
     
         13 . A processor comprising:
 a transmitter of a parallel input-output (I/O) link, the transmitter having a pull-up driver, a pull-down driver, and an equalizer coupled to the pull-up and pull-down drivers; and   pull-up driver and pull-down driver compensation units to determine codes for first impedance of the pull-up driver and a second impedance of the pull-down driver respectively,   wherein the equalizer is disabled when the pull-up driver and pull-down driver compensation units are determining codes for the first and second impedances.   
     
     
         14 . The processor of  claim 13 , wherein the first impedance is independently controllable from control of the second impedance. 
     
     
         15 . The processor of  claim 13 , wherein the equalizer is operable to be trained to deemphasize a signal driven on a node, coupled to the pull-up driver, pull-down driver, and the equalizer, while maintaining the first and second impedances substantially constant. 
     
     
         16 . The processor of  claim 13 , wherein:
 the pull-up driver compensation unit is operable to determine a code for setting a pull-up granularity for de-emphasizing the signal by the equalizer, wherein the code, for setting a pull-up granularity for de-emphasizing the signal by the equalizer, is programmable; and   the pull-down driver compensation unit is operable to determine a code for setting a pull-down granularity for de-emphasizing the signal by the equalizer, wherein the code, for setting a pull-down granularity for de-emphasizing the signal by the equalizer, is programmable.   
     
     
         17 . The processor of  claim 13 , wherein the first and second impedances are substantially constant during a period when the equalizer is in non-equalization mode or equalization mode. 
     
     
         18 . A method comprising:
 initializing non-equalization codes for a pull-up driver and a pull-down driver respectively;   setting a reference signal to correspond to a target impedance value for the pull-up and pull-down drivers;   incrementing the initialized non-equalization codes for the pull-up and pull-down drivers to adjust impedances of the pull-up and pull-down drivers;   determining whether the impedances corresponding to the pull-up and pull-down drivers, respectively, are substantially equal to the target impedance value;   setting the reference signal to correspond to an equalization granularity level for an equalizer which coupled to the pull-up and pull-down drivers; and   incrementing equalization codes for the equalizer when it is determined that the equalization granularity level for the equalizer is not met.   
     
     
         19 . The method of  claim 16 , wherein the equalizer is disabled when determining whether the impedances corresponding to the pull-up and pull-down drivers, respectively, are substantially equal to the target impedance value, and wherein the equalizer is enabled after determining that the impedances corresponding to the pull-up and pull-down drivers, respectively, are substantially equal to the target impedance value. 
     
     
         20 . A system comprising:
 a memory unit;   a processor, coupled to the memory unit, the processor including:
 a pull-up driver with a first impedance, the pull-up driver coupled to a node; 
 a pull-down driver with a second impedance, the pull-down driver coupled to the node; and 
 an equalizer coupled to the pull-up and pull-down drivers, wherein the equalizer is operable to be trained to deemphasize a signal driven on the node while maintaining the first and second impedances substantially constant; 
   a wireless interface to allow the processor to communicate with another device; and   a display unit.   
     
     
         21 . The system of  claim 20 , wherein the equalizer is part of a parallel input-output (I/O) link. 
     
     
         22 . The system of  claim 20 , wherein the first impedance is independently controllable from control of the second impedance. 
     
     
         23 . The system of  claim 20 , wherein the first and second impedances are substantially constant during a period when the equalizer is in non-equalization mode or equalization mode.