Semiconductor light emitting element and method for manufacturing same
Abstract
According to one embodiment, a semiconductor light emitting element includes a first semiconductor layer, a second semiconductor layer, and a light emitting unit. The first semiconductor layer includes an n-type impurity having a first concentration. The second semiconductor layer includes a p-type impurity. The light emitting unit is provided between the first and second semiconductor layers. The light emitting unit includes a first barrier layer, a second barrier layer provided between the first barrier layer and the second semiconductor layer, a third barrier layer provided between the second barrier layer and the second semiconductor layer, a first well layer provided between the first and second barrier layers, and a second well layer provided between the second and third barrier layers. A plane including a boundary between the first barrier layer and the first well layer intersects a plane including a (0001) plane of the first semiconductor layer.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor light emitting element, comprising:
a first semiconductor layer including an n-type impurity having a first concentration; a second semiconductor layer including a p-type impurity; and a light emitting unit provided between the first semiconductor layer and the second semiconductor layer, the light emitting unit including
a first barrier layer,
a second barrier layer provided between the first barrier layer and the second semiconductor layer, the second barrier layer including an n-type impurity having a second concentration higher than the first concentration,
a third barrier layer provided between the second barrier layer and the second semiconductor layer,
a first well layer provided between the first barrier layer and the second barrier layer, and
a second well layer provided between the second barrier layer and the third barrier layer,
a plane including a boundary between the first barrier layer and the first well layer intersecting a plane including a (0001) plane of the first semiconductor layer.
2 . The element according to claim 1 , wherein an angle between the boundary and the (0001) plane is not less than 15 degrees and not more than 165 degrees.
3 . The element according to claim 1 , wherein the boundary is tilted with respect to the (0001) plane.
4 . The element according to claim 1 , wherein the second concentration is not less than 2.0×10 18 per cubic centimeter.
5 . The element according to claim 1 , wherein the second concentration is not less than 5.0×10 18 per cubic centimeter.
6 . The element according to claim 1 , wherein a thickness of the second barrier layer is not less than 3.0 nanometers and not more than 7.0 nanometers.
7 . The element according to claim 1 , wherein the first barrier layer and the third barrier layer have thicknesses not less than 3.0 nanometers and not more than 7.0 nanometers.
8 . The element according to claim 1 , wherein the first well layer and the second well layer have thicknesses not less than 3.5 nanometers and not more than 7.5 nanometers.
9 . A method for manufacturing a semiconductor light emitting element, comprising:
forming a first semiconductor layer on a substrate, the first semiconductor layer including an n-type impurity having a first concentration; forming a light emitting unit on the first semiconductor layer, the light emitting unit including a first barrier layer, a second barrier layer provided on the first barrier layer, a third barrier layer provided on the second barrier layer, a first well layer provided between the first barrier layer and the second barrier layer, and a second well layer provided between the second barrier layer and the third barrier layer, the second barrier layer including an n-type impurity having a second concentration higher than the first concentration; and forming a second semiconductor layer on the light emitting unit, the second semiconductor layer including a p-type impurity, a plane including a boundary between the first barrier layer and the first well layer intersecting a plane including a (0001) plane of the first semiconductor layer.
10 . The method according to claim 9 , wherein an angle between the boundary and the (0001) plane is not less than 15 degrees and not more than 165 degrees.
11 . The method according to claim 9 , wherein the boundary is tilted with respect to the (0001) plane.
12 . The method according to claim 9 , wherein the second concentration is not less than 2.0×10 18 per cubic centimeter.
13 . The method according to claim 9 , wherein the second concentration is not less than 5.0×10 18 per cubic centimeter.
14 . The method according to claim 9 , wherein a thickness of the second barrier layer is not less than 3.0 nanometers and not more than 7.0 nanometers.
15 . The method according to claim 9 , wherein the first barrier layer and the third barrier layer have thicknesses not less than 3.0 nanometers and not more than 7.0 nanometers.
16 . The method according to claim 9 , wherein the first well layer and the second well layer have thicknesses not less than 3.5 nanometers and not more than 7.5 nanometers.Join the waitlist — get patent alerts
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