US2015270375A1PendingUtilityA1

Method of manufacture for a semiconductor device

Assignee: MAXPOWER SEMICONDUCTOR INCPriority: Jan 9, 2007Filed: Jan 22, 2015Published: Sep 24, 2015
Est. expiryJan 9, 2027(~0.4 yrs left)· nominal 20-yr term from priority
H10P 30/222H10P 95/90H10P 50/642H10P 30/225H10P 30/20H10P 14/69433H10P 14/69215H10P 14/6518H10P 14/29H10D 64/013H10W 10/17H10W 10/014H10D 30/603H10D 30/63H10D 30/663H10D 30/66H10D 30/0297H10D 64/118H10D 62/116H10D 84/0195H10D 30/668H10D 84/038H10D 64/516H10D 64/513H10D 62/393H10D 62/157H10D 62/151H10D 62/127H10D 62/126H10D 62/106H10D 62/104H10D 62/115H10D 62/111H10D 30/665H10D 30/0217H10D 30/025H01L 21/265H01L 29/0634H01L 29/66734H01L 21/0217H01L 21/76224H01L 21/30604H01L 21/02164H01L 29/0649H01L 21/02321H01L 21/324H10P 14/63
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Claims

Abstract

A method of manufacturing a semiconductor device includes providing a semiconductor layer of a first conductivity type and forming a semiconductor layer of a second conductivity type thereon. The method also includes forming an insulator layer on the semiconductor layer of the second conductivity type, etching a trench into at least the semiconductor layer of the second conductivity type, and forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type. The method further includes implanting ions into the thermal oxide layer, forming a second insulator layer, removing the second insulator layer from a portion of the trench, and forming an oxide layer in the trench and on the epitaxial layer. Moreover, the method includes forming a material in the trench, forming a second gate oxide layer over the material, and patterning the second gate oxide layer.

Claims

exact text as granted — not AI-modified
1 - 20 . (canceled) 
     
     
         21 . A method of manufacturing a semiconductor device, the method comprising:
 providing a semiconductor layer of a first conductivity type;   forming a semiconductor layer of a second conductivity type on the semiconductor layer of the first conductivity type;   forming an insulator layer on the semiconductor layer of the second conductivity type;   etching a trench into at least the semiconductor layer of the second conductivity type;   forming a thermal oxide layer in the trench and on the semiconductor layer of the second conductivity type;   implanting ions into the thermal oxide layer;   forming a second insulator layer, thereby filling at least a portion of the trench;   removing the second insulator layer from a portion of the trench;   forming an oxide layer in the trench and on the epitaxial layer;   forming a material in the trench;   forming one or more device regions;   forming a third insulating layer over the material;   patterning the third insulating layer; and forming a source metal layer;   wherein the second insulator layer comprises a multilayer dielectric stack.   
     
     
         22 . The method of  claim 21  wherein the multilayer dielectric stack comprises:
 a layer of silicon oxide; 
 a layer of silicon nitride; and 
 a second layer of silicon oxide. 
 
     
     
         23 - 44 . (canceled) 
     
     
         45 . A method of manufacturing semiconductor device the method comprising:
 providing a semiconductor layer of a first conductivity type;   forming a semiconductor layer of a second conductivity type on the semiconductor layer of the first conductivity type;   forming an insulator layer on the semiconductor layer of the second conductivity type;   etching one or more trenches into at least the semiconductor layer of the second conductivity type;   forming a second insulator layer in the one or more trenches;   implanting ions into the second insulator layer;   forming a third insulator layer, thereby filling at least a portion of the one or more trenches;   etching an additional trench into at least the semiconductor layer of the second conductivity type;   forming a gate oxide layer in the additional trench;   forming a gate material in the additional trench;   forming one or more device regions; and   forming a source metal layer;   wherein the one or more trenches extend to the semiconductor layer of the first conductivity type.   
     
     
         46 . The method of  claim 45  wherein the second insulator layer comprises a thermal oxide layer. 
     
     
         47 . The method of  claim 45  wherein forming a third insulator layer completely fills the one or more trenches. 
     
     
         48 . The method of  claim 45  wherein the insulator layer comprises a multilayer dielectric stack. 
     
     
         49 . The method of  claim 48  wherein the multilayer dielectric stack comprises:
 a layer of silicon oxide; and 
 a layer of silicon nitride. 
 
     
     
         50 . A method of manufacturing a semiconductor device, the method comprising:
 providing a semiconductor layer of a first conductivity type;   forming a semiconductor layer of a second conductivity type on the semiconductor layer of the first conductivity type;   forming an insulator layer on the semiconductor layer of the second conductivity type;   etching a trench into at least the semiconductor layer of the second conductivity type;   forming an oxide layer in the trench and on the semiconductor layer of the second conductivity type;   implanting ions into the oxide layer;   forming a second insulator layer, thereby filling the trench;   forming one or more device regions; and   forming a metal layer;   wherein the trench extends to the semiconductor layer of the first conductivity type.   
     
     
         51 . (canceled) 
     
     
         52 . The method of  claim 50  wherein the ions comprise cesium ions. 
     
     
         53 . The method of  claim 52  further comprising: capping the second insulator layer; and performing a thermal treatment to anneal the cesium ions. 
     
     
         54 . The method of  claim 50  wherein the ions comprise iodine, bromine, chromium, aluminum, or chlorine ions. 
     
     
         55 . The method of  claim 54  further comprising:
 capping the second insulator layer; and 
 performing a thermal treatment to anneal the iodine, bromine, chromium, aluminum, or chlorine ions. 
 
     
     
         56 . The method of  claim 50  wherein the second insulator layer comprises a multilayer dielectric stack.

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