Semiconductor device including superlattice sige/si fin structure

Abstract

A semiconductor device includes a semiconductor-on-insulator substrate having an insulator layer, and at least one silicon germanium (SiGe) fin having a superlattice structure. The SiGe fin is formed on an upper surface of the insulator layer. A gate stack is formed on an upper surface of the at least one silicon germanium fin. The gate stack includes first and second opposing spacers defining a gate length therebetween. First and second epitaxial source/drain structures are formed on the insulator layer. The first and second epitaxial source/drain structures extend beneath the spacer to define a silicon germanium gate channel beneath the gate stack.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor-on-insulator substrate including an insulator layer;   at least one fin having a superlattice structure, the at least one fin formed on an upper surface of the insulator layer;   a gate stack formed on an upper surface of the at least one fin, the gate stack including first and second opposing spacers defining a gate length therebetween; and   first and second epitaxial source/drain structures formed on the insulator layer and extending beneath the spacer to define a superlattice gate channel beneath the gate stack.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the superlattice structure is a superlattice silicon germanium/silicon (SiGe/Si) structure, and wherein the superlattice gate channel is a superlattice SiGe/Si gate channel beneath the gate stack. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the spacers are offset with respect to the first and second epitaxial source/drain structures. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the first and second epitaxial source/drain structures include respective source/drain extension portions overlapping the spacer and extending beneath the gate stack. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the SiGe/Si gate channel is interposed between the source/drain extension portions. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the gate stack includes a metal gate interposed between the spacer. 
     
     
         7 . The semiconductor device of  claim 6 , further comprising at least one gate layer interposed between the metal gate, the source/drain extension portions, and the SiGe/Si gate channel. 
     
     
         8 . The semiconductor device of  claim 6 , wherein the at least one gate layer is interposed between the metal gate and the SiGe/Si gate channel. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the at least one gate layer includes a high dielectric material atop the silicon germanium gate channel. 
     
     
         10 . The semiconductor device of  claim 9 , wherein the at least one gate layer includes a metal contact layer formed on the high dielectric material. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the metal gate is formed from tungsten. 
     
     
         12 . The semiconductor device of  claim 11 , wherein high dielectric material is formed from hafnium oxide. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the metal contact layer is formed from one of titanium nitride or titanium carbide.