Semiconductor devices with a replacement gate structure having a recessed channel

Abstract

Disclosed herein are various methods of forming replacement gate structures with a recessed channel region. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, removing the sacrificial gate structure to thereby define an initial gate opening having sidewalls and to expose a surface of the substrate and performing an etching process on the exposed surface of the substrate to define a recessed channel in the substrate. The method includes the additional steps of forming a sidewall spacer within the initial gate opening on the sidewalls of the initial gate opening to thereby define a final gate opening and forming a replacement gate structure in the final gate opening.

1 .- 14 . (canceled) 
     
     
         15 . A device, comprising:
 a semiconducting substrate having an upper surface;   a recessed channel formed in said substrate, said recessed channel having an upper surface that is at a level that is below a level of said upper surface of said substrate;   a tapered surface extending between said upper surface of said recessed channel and said upper surface of said substrate;   a gate insulation layer formed on said recessed channel; and   a gate electrode formed above said gate insulation layer.   
     
     
         16 . The device of  claim 15 , wherein said upper surface of said recessed channel is positioned at a depth of 10-30 nm below said upper surface of said substrate. 
     
     
         17 . The device of  claim 15 , further comprising a plurality of source/drain regions, each of which has an upper surface that is positioned at a level that is above said upper surface of said recessed channel. 
     
     
         18 . The device of  claim 15 , wherein said gate electrode has a top surface and a bottom surface and wherein said top surface is wider than said bottom surface. 
     
     
         19 . The device of  claim 15 , further comprising a first spacer positioned around said gate electrode. 
     
     
         20 . The device of  claim 19 , wherein said first spacer is thicker at a bottom of said first spacer than at a top of said first spacer. 
     
     
         21 . The device of  claim 19 , further comprising a second spacer positioned laterally adjacent said first spacer, said second spacer having a bottom surface that is positioned at a level this is equal to or above a level of said upper surface of said substrate, wherein a portion of said first spacer extends laterally under at least a portion of said bottom surface of said second spacer. 
     
     
         22 . The device of  claim 19 , wherein a lateral distance between a top of said first spacer on opposite sides of said gate electrode is greater than a lateral distance between a bottom of said first spacer on opposite sides of said gate electrode. 
     
     
         23 . The device of  claim 15 , wherein said substrate comprises silicon. 
     
     
         24 . The device of  claim 15 , wherein said gate insulation layer is a high-k insulating material and said gate electrode is a comprised of a layer of metal. 
     
     
         25 . The device of  claim 15 , further comprising a plurality of sigma-shaped source/drain regions positioned at least partially in said substrate, said sigma-shaped source/drain regions having peak inward penetration toward said recessed channel, wherein a vertical level of said peak inward penetration is approximately level with said upper surface of said recessed channel. 
     
     
         26 . The device of  claim 15 , wherein said tapered surface is positioned in a <111> plane of said substrate. 
     
     
         27 . The device of  claim 21 , wherein said portion of said first spacer extends laterally under at least said portion of said bottom surface of said second spacer by a distance of up to 5 nm. 
     
     
         28 . A device, comprising:
 a semiconducting substrate having an upper surface;   a recessed channel formed in said substrate, said recessed channel having an upper surface that is at a level that is below a level of said upper surface of said substrate;   a gate insulation layer formed on said recessed channel;   a gate electrode formed above said gate insulation layer;   a first spacer positioned around said gate electrode; and   a second spacer positioned laterally adjacent said first spacer, said second spacer having a bottom surface that is positioned at a level that is equal to or above a level of said upper surface of said substrate, wherein a portion of said first spacer extends laterally under at least a portion of said bottom surface of said second spacer.   
     
     
         29 . The device of  claim 28 , further comprising a plurality of source/drain regions, each of which has an upper surface that is positioned at a level that is above said upper surface of said recessed channel. 
     
     
         30 . The device of  claim 28 , wherein said gate electrode has a top surface and a bottom surface and wherein said top surface is wider than said bottom surface. 
     
     
         31 . The device of  claim 28 , wherein said first spacer is thicker at a bottom of said first spacer than at a top of said first spacer. 
     
     
         32 . The device of  claim 31 , wherein a lateral distance between said top of said first spacer on opposite sides of said gate electrode is greater than a lateral distance between said bottom of said first spacer on opposite sides of said gate electrode. 
     
     
         33 . The device of  claim 28 , further comprising a plurality of sigma-shaped source/drain regions positioned at least partially in said substrate, said sigma-shaped source/drain regions having peak inward penetration toward said recessed channel, wherein a vertical level of said peak inward penetration is approximately level with said upper surface of said recessed channel. 
     
     
         34 . The device of  claim 28 , wherein said portion of said first spacer extends laterally under at least said portion of said bottom surface of said second spacer by a distance of up to 5 nm. 
     
     
         35 . A device, comprising:
 a silicon substrate having an upper surface;   a recessed channel formed in said substrate, said recessed channel having an upper surface that is at a level that is below a level of said upper surface of said substrate;   a tapered surface extending between said upper surface of said recessed channel and said upper surface of said substrate;   a gate insulation layer formed on said recessed channel;   a gate electrode formed above said gate insulation layer;   a first spacer positioned around said gate electrode;   a second spacer positioned laterally adjacent said first spacer, said second spacer having a bottom surface that is positioned at a level that is equal to or above a level of said upper surface of said substrate, wherein a portion of said first spacer extends laterally under at least a portion of said bottom surface of said second spacer; and   a plurality of sigma-shaped source/drain regions positioned at least partially in said substrate, said sigma-shaped source/drain regions having peak inward penetration toward said recessed channel, wherein a vertical level of said peak inward penetration is approximately level with said upper surface of said recessed channel.   
     
     
         36 . The device of  claim 35 , wherein said upper surface of said recessed channel is positioned at a depth of 10-30 nm below said upper surface of said substrate. 
     
     
         37 . The device of  claim 36 , wherein said gate electrode has a top surface and a bottom surface and wherein said top surface is wider than said bottom surface. 
     
     
         38 . The device of  claim 37 , wherein a lateral distance between a top of said first spacer on opposite sides of said gate electrode is greater than a lateral distance between a bottom of said first spacer on opposite sides of said gate electrode. 
     
     
         39 . The device of  claim 35 , wherein said tapered surface is positioned in a <111> plane of said substrate. 
     
     
         40 . The device of  claim 39 , wherein said portion of said first spacer extends laterally under at least said portion of said bottom surface of said second spacer by a distance of up to 5 nm.