Opportunistic placement of ic test strucutres and/or e-beam target pads in areas otherwise used for filler cells, tap cells, decap cells, scribe lines, and/or dummy fill, as well as product ic chips containing same

Abstract

Product ICs/wafers include additional diagnostic, test, or monitoring structures opportunistically placed in filler cell positions, within tap cells, within decap cells, within scribe line areas, and/or within dummy fill regions. Improved fabrication processes utilize data from such structure(s) in wafer disposition decisions, rework decisions, process control, yield learning, or fault diagnosis.

1 . An IC fabrication process, comprising at least the following steps:
 subjecting a product IC wafer to initial fabrication steps;   obtaining e-beam excited measurements, without continuously scanning, from a plurality of test structures by selectively sampling fewer than ten pixels from an e-beam pad associated with each of said test structures; and, based, at least in part, on measurements obtained from said test structures, selectively subjecting the wafer to additional fabrication steps.   
     
     
         2 . An IC fabrication process, as defined in  claim 1 , wherein obtaining measurements comprises selectively targeting e-beam target pads having an asymmetric aspect ratio. 
     
     
         3 . An IC fabrication process, as defined in  claim 1 , wherein obtaining measurements involves obtaining only a single pixel measurement from each targeted e-beam pad. 
     
     
         4 . An IC fabrication process, as defined in  claim 1 , wherein selectively subjecting comprises determining whether to rework one or more of the initial fabrication steps. 
     
     
         5 . An IC fabrication process, as defined in  claim 1 , wherein selectively subjecting comprises determining whether or not to perform the additional fabrication steps. 
     
     
         6 . An IC fabrication process, comprising at least the following steps:
 subjecting a product IC wafer to initial fabrication steps;   obtaining e-beam excited measurements from a plurality of test structures by selectively targeting, using an e-beam spot with an elongated major axis, an e-beam pad associated with each of said test structures; and,   based, at least in part, on measurements obtained from said test structures, selectively subjecting the wafer to additional fabrication steps.   
     
     
         7 . An IC fabrication process, as defined in  claim 6 , wherein each of the targeted e-beam pads has at least one of its dimensions matched to the elongated major axis of the e-beam spot, so as to maximize scanning efficiency. 
     
     
         8 . An IC fabrication process, as defined in  claim 6 , wherein each of the targeted e-beam pads has a first one of its dimensions matched to the elongated major axis of the e-beam spot, and wherein at least some of the targeted e-beam pads vary in a second dimension perpendicular to said first dimension. 
     
     
         9 . An IC fabrication process, as defined in  claim 6 , wherein each of the targeted e-beam pads is positioned along a linear scan line, and wherein the elongated major axis of the e-beam spot is oriented perpendicular to the scan line. 
     
     
         10 . An IC fabrication process, as defined in  claim 6 , wherein obtaining measurements involves obtaining fewer than ten pixel measurements from each targeted e-beam pad. 
     
     
         11 . An IC fabrication process, as defined in  claim 10 , wherein obtaining measurements involves obtaining only a single pixel measurement from each targeted e-beam pad. 
     
     
         12 . An IC fabrication process, as defined in  claim 6 , wherein selectively subjecting comprises determining whether to rework one or more of the initial fabrication steps. 
     
     
         13 . An IC fabrication process, as defined in  claim 6 , wherein selectively subjecting comprises determining whether or not to perform the additional fabrication steps. 
     
     
         14 . An IC fabrication process, comprising at least the following steps:
 subjecting a product IC wafer to initial fabrication steps;   obtaining e-beam excited measurements from a plurality of test structures by selectively targeting, along a linear scan direction, an e-beam pad associated with each of said test structures, wherein each targeted e-beam pad comprises a plurality of electrically connected, elongated metal segments; and,   based, at least in part, on measurements obtained from said test structures, selectively subjecting the wafer to additional fabrication steps.   
     
     
         15 . An IC fabrication process, as defined in  claim 14 , wherein each of the targeted e-beam pads has at least two elongated metal segments that are identical in size and shape. 
     
     
         16 . An IC fabrication process, as defined in  claim 14 , wherein obtaining measurements involves obtaining fewer than ten pixel measurements from each targeted e-beam pad. 
     
     
         17 . An IC fabrication process, as defined in  claim 16 , wherein obtaining measurements involves obtaining only a single pixel measurement from each targeted e-beam pad. 
     
     
         18 . An IC fabrication process, as defined in  claim 14 , wherein obtaining measurements involves selectively targeting, using an e-beam spot with an elongated major axis oriented perpendicular to the linear scan direction. 
     
     
         19 . An IC fabrication process, as defined in  claim 14 , wherein selectively subjecting comprises determining whether to rework one or more of the initial fabrication steps. 
     
     
         20 . An IC fabrication process, as defined in  claim 14 , wherein selectively subjecting comprises determining whether or not to perform the additional fabrication steps.