Method for reading a third-dimensional embedded re-writeable non-volatile memory and registers

Abstract

A non-volatile register includes register logic connected with first and second ends of a memory element. The register logic is positioned below the memory element. The memory element may be a two-terminal memory element configured to store data as a plurality of conductivity profiles that can be non-destructively determined by applying a read voltage across the two terminals. New data can be written to the two-terminal memory element by applying a write voltage of a predetermined magnitude and/or polarity across the two terminals. The two-terminal memory element retains stored data in the absence of power. A reference element including a structure that is identical or substantially identical to the two-terminal memory element may be used to generate a reference signal for comparisons during read operations.

1 - 15 . (canceled) 
     
     
         16 . A method, comprising:
 applying a voltage across a memory element configured to store data as a plurality of conductivity profiles and further configured to retain the data in the absence of electrical power;   reading a current associated with the memory element based, at least in part, on the voltage; and   comparing the current with a reference current to define a datum stored in the memory element;   wherein the memory element comprises:
 a conductive oxide including mobile oxygen ions; and 
 an electrolytic tunnel barrier electrically in series with the conductive oxide. 
   
     
     
         17 . The method of  claim 16 , wherein the electrolytic tunnel barrier comprises a thickness that is less than approximately 50 angstroms. 
     
     
         18 . The method of  claim 16 , wherein said comparing the current with a reference current comprises sensing a difference between the current and the reference current. 
     
     
         19 . The method of  claim 16 , wherein:
 the memory element is integrally fabricated directly above a silicon substrate;   the silicon substrate comprises circuitry fabricated on the silicon substrate; and   the circuitry comprises a register logic electrically coupled with the memory element.   
     
     
         20 . The method of  claim 19 , wherein the memory element is embedded in a memory plane that is integrally fabricated directly above and in direct contact with the silicon substrate. 
     
     
         21 . The method of  claim 20 , wherein:
 the memory plane comprises a two-terminal cross-point array having a plurality of conductive array lines;   the memory element is positioned between a cross-point of a unique pair from the plurality of conductive array lines;   a first terminal and a second terminal of the memory element are electrically coupled with the unique pair of conductive array lines;   the memory element is directly electrically in series with the unique pair of conductive array lines; and   the unique pair of conductive array lines electrically couple the memory element with the register logic.   
     
     
         22 . The method of  claim 16 , further comprising generating the reference current using a reference element. 
     
     
         23 . The method of  claim 16 , further comprising storing a result of said comparing the current with a reference current. 
     
     
         24 . The method of  claim 16 , further comprising substantially synchronizing said comparing the current with a reference current to an enable signal or a clock signal. 
     
     
         25 . A method, comprising:
 applying a read voltage across a memory element configured to store data as a plurality of conductivity profiles;   reading a current through the memory element in response to said applying a read voltage across a memory element;   determining a difference between the current and a reference current; and   defining a datum stored in the memory element based, at least in part, on the difference;   wherein the memory element comprises:   a conductive oxide including mobile oxygen ions; and   an electrolytic tunnel barrier electrically in series with the conductive oxide.   
     
     
         26 . The method of  claim 25 , wherein the electrolytic tunnel barrier comprises a thickness that is less than approximately 50 angstroms. 
     
     
         27 . The method of  claim 25 , wherein:
 the memory element is integrally fabricated directly above a silicon substrate;   the silicon substrate comprises circuitry fabricated on the silicon substrate; and   the circuitry comprises a register logic electrically coupled with the memory element.   
     
     
         28 . The method of  claim 27 , wherein the memory element is embedded in a memory plane that is integrally fabricated directly above and in direct contact with the silicon substrate. 
     
     
         29 . The method of  claim 28 , wherein:
 the memory plane comprises a two-terminal cross-point array having a plurality of conductive array lines;   the memory element is positioned between a cross-point of a unique pair from the plurality of conductive array lines;   a first terminal and a second terminal of the memory element are electrically coupled with the unique pair of conductive array lines;   the memory element is directly electrically in series with the unique pair of conductive array lines; and   the unique pair of conductive array lines electrically couple the memory element with the register logic.   
     
     
         30 . The method of  claim 25 , further comprising substantially synchronizing said determining a difference between the current and a reference current to an enable signal or a clock signal. 
     
     
         31 . A system, comprising:
 a voltage circuit configured to apply a voltage across terminals of a memory element configured to store data as a plurality of conductivity profiles and further configured to retain the data in the absence of electrical power;   a sensing circuit configured to sense a current through the memory element in response to the voltage; and   a comparing circuit configured to define a datum stored in the memory element by comparing the current and a reference current;   wherein the memory element comprises:
 a conductive oxide including mobile oxygen ions; and 
 an electrolytic tunnel barrier electrically in series with the conductive oxide. 
   
     
     
         32 . The system of  claim 31 , wherein the electrolytic tunnel barrier comprises a thickness that is less than approximately 50 angstroms. 
     
     
         33 . The system of  claim 33 , wherein:
 the memory element is integrally fabricated directly above a silicon substrate;   the silicon substrate comprises circuitry fabricated on the silicon substrate; and   the circuitry comprises a register logic electrically coupled with the memory element.   
     
     
         34 . The system of  claim 33 , wherein:
 the memory element is embedded in a memory plane that is integrally fabricated directly above and in direct contact with the silicon substrate;   the memory plane comprises a two-terminal cross-point array having a plurality of conductive array lines;   the memory element is positioned between a cross-point of a unique pair from the plurality of conductive array lines;   a first terminal and a second terminal of the memory element are electrically coupled with the unique pair of conductive array lines;   the memory element is directly electrically in series with the unique pair of conductive array lines; and   the unique pair of conductive array lines electrically couple the memory element with the register logic.   
     
     
         35 . The system of  claim 31 , further comprising a synchronizing circuit configured to substantially synchronize said comparing the current and a reference current to an enable signal or a clock signal.