Semiconductor Device Having a Charge Compensation Region

Abstract

A semiconductor device includes a semiconductor material of a first conductivity type, a body region of a second (opposite) conductivity type extending into the semiconductor material from a main surface of the semiconductor material, a source region of the first conductivity type disposed in the body region, and a channel region extending laterally in the body region from the source region along the main surface. A charge compensation region of the second conductivity type can be provided under the body region which extends in a direction parallel to the main surface and terminates prior to a pn-junction between the source and body regions at the main surface, and/or an additional region of the first conductivity type which has at least one peak doping concentration each of which occurs deeper in the semiconductor material from the main surface than a peak doping concentration of the device channel region.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a semiconductor material of a first conductivity type having a main surface;   a body region of a second conductivity type opposite the first conductivity type extending into the semiconductor material from the main surface;   a source region of the first conductivity type disposed in the body region;   a channel region extending in the body region from the source region along the main surface of the semiconductor material;   a charge compensation region of the second conductivity type disposed under the body region; and   an additional region of the first conductivity type disposed in the semiconductor material adjacent the body region, the additional region having a peak doping concentration which occurs deeper in the semiconductor material from the main surface than a peak doping concentration of the channel region.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising a gate dielectric disposed on the main surface of the semiconductor material and a gate conductor disposed on the gate dielectric, wherein the gate dielectric has the same thickness over the additional region and the channel region. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the additional region does not extend to the main surface. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the additional region has a single peak doping concentration and a doping profile of the additional region is substantially the same above and below the single peak doping concentration. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the charge compensation region extends in a direction parallel to the main surface of the semiconductor material and terminates prior to a pn-junction between the source region and the body region at the main surface. 
     
     
         6 . A method of manufacturing a semiconductor device, the method comprising:
 forming a semiconductor material of a first conductivity type having a main surface;   forming a body region of a second conductivity type opposite the first conductivity type which extends into the semiconductor material from the main surface;   forming a source region of the first conductivity type in the body region;   forming a channel region which extends in the body region from the source region along the main surface of the semiconductor material;   forming a charge compensation region of the second conductivity type under the body region; and   forming an additional region of the first conductivity type in the semiconductor material adjacent the body region, the additional region having a peak doping concentration which occurs deeper in the semiconductor material from the main surface than a peak doping concentration of the channel region.   
     
     
         7 . The method according to  claim 6 , further comprising forming a gate dielectric on the main surface of the semiconductor material and a gate conductor on the gate dielectric, the gate dielectric having the same thickness over the additional region and the channel region. 
     
     
         8 . The method according to  claim 6 , wherein forming the additional region comprises:
 implanting a dopant species of the first conductivity type into an active device region of the semiconductor material at an implantation energy which yields a single peak concentration level of the implanted dopant species deep enough below the main surface of the semiconductor material so that the additional region does not reach the main surface once formed; and   diffusing the implanted dopant species to form the additional region which does not reach the main surface.   
     
     
         9 . The method according to  claim 6 , wherein forming the charge compensation region comprises:
 forming a mask with an opening over the source region;   etching a groove through the source region into the body region via the opening in the mask;   implanting a dopant species of the second conductivity type into the semiconductor material under the body region via the groove; and   thermally treating the semiconductor material to form the charge compensation region.   
     
     
         10 . A semiconductor device, comprising:
 a semiconductor material of a first conductivity type having a main surface;   a body region of a second conductivity type opposite the first conductivity type extending into the semiconductor material from the main surface;   a source region of the first conductivity type disposed in the body region;   a groove extending from the main surface of the semiconductor material through the source region into the body region; and   a charge compensation region of the second conductivity type disposed under the body region in alignment with the groove, the charge compensation region extending in a direction parallel to the main surface of the semiconductor material and terminating prior to a pn-junction between the source region and the body region at the main surface.   
     
     
         11 . The semiconductor device according to  claim 10 , further comprising a gate dielectric disposed on the main surface of the semiconductor material and a gate conductor disposed on the gate dielectric, wherein the charge compensation region does not extend under the gate conductor. 
     
     
         12 . The semiconductor device according to  claim 10 , further comprising:
 oxide disposed on the main surface of the semiconductor material in an edge region of the semiconductor device, the silicon region under the oxide being devoid of the source and body regions;   grooves extending into the oxide toward the main surface of the semiconductor material; and   additional charge compensation regions of the second conductivity type disposed in the semiconductor material under and aligned with the grooves in the oxide.   
     
     
         13 . The semiconductor device according to  claim 12 , wherein the additional charge compensation regions are arranged in a checkerboard pattern. 
     
     
         14 . The semiconductor device according to  claim 12 , wherein the additional charge compensation regions are formed as stripes disposed at an angle with respect to the charge compensation region under the body region. 
     
     
         15 . The semiconductor device according to  claim 10 , further comprising:
 a channel region extending laterally in the body region from the source region along the main surface of the semiconductor material; and   an additional region of the first conductivity type disposed in the semiconductor material adjacent the body region, the additional region having a peak doping concentration which occurs deeper in the semiconductor material from the main surface than a peak doping concentration of the channel region.   
     
     
         16 . A method of manufacturing a semiconductor device, the method comprising:
 forming a semiconductor material of a first conductivity type having a main surface;   forming a body region of a second conductivity type opposite the first conductivity type which extends into the semiconductor material from the main surface;   forming a source region of the first conductivity type in the body region;   forming a groove extending from the main surface of the semiconductor material through the source region into the body region; and   forming a charge compensation region of the second conductivity type under the body region in alignment with the groove, the charge compensation region extending in a direction parallel to the main surface of the semiconductor material and terminating prior to a pn-junction between the source region and the body region at the main surface.   
     
     
         17 . The method according to  claim 16 , further comprising:
 forming an oxide on the main surface of the semiconductor material in an edge region of the semiconductor device, the silicon region under the oxide being devoid of the source and body regions;   forming grooves which extend into the oxide toward the main surface of the semiconductor material; and   forming additional charge compensation regions of the second conductivity type in the semiconductor material under and aligned with the grooves in the oxide.   
     
     
         18 . The method according to  claim 16 , wherein forming the groove and the charge compensation region comprises:
 forming a mask on the semiconductor material with an opening over the source region;   etching the groove through the source region into the body region via the opening in the mask;   implanting a dopant species of the second conductivity type into the semiconductor material under the body region via the groove; and   thermally treating the implant to form the charge compensation region.   
     
     
         19 . The method according to  claim 18 , further comprising implanting the dopant species of the second conductivity type into the body region via the opening in the mask to form an implanted body contact region prior to implanting the dopant species used to form the charge compensation region, and wherein the dopant species used to form the charge compensation region is implanted after the implanted body contact region is formed and without an intermediate anneal. 
     
     
         20 . The method according to  claim 18 , wherein the implanting of the dopant species yields implant tails which extend to the main surface of the semiconductor material, and wherein the thermal treatment is performed so that the implant tails are not driven under the source region. 
     
     
         21 . The method according to  claim 18 , wherein forming the mask with an opening over the source region comprises:
 forming an insulator on the main surface of the semiconductor material and a resist on the insulator;   patterning the resist to form the opening in the insulator; and   removing the resist after the opening is formed in the insulator and before the dopant species is implanted into the semiconductor material under the body region via the opening in the insulator.   
     
     
         22 . The method according to  claim 18 , wherein forming the mask with an opening over the source region comprises:
 forming an insulator on the main surface of the semiconductor material and a resist on the insulator;   patterning the resist to form the opening in the insulator; and   leaving the resist in place after the opening is formed in the insulator and before the dopant species is implanted into the semiconductor material under the body region via the opening in the resist and insulator.   
     
     
         23 . The method according to  claim 16 , further comprising:
 forming a channel region which extends laterally in the body region from the source region along the main surface of the semiconductor material; and   forming an additional region of the first conductivity type in the semiconductor material adjacent the body region, the additional region having a peak doping concentration which occurs deeper in the semiconductor material from the main surface than a peak doping concentration of the channel region.   
     
     
         24 . The method according to  claim 23 , wherein forming the charge compensation region comprises:
 implanting a dopant species of the second conductivity type into the semiconductor material under the body region via an opening in a mask which exposes the groove, the implanting of the dopant species yielding implant tails which extend to the main surface of the semiconductor material; and   annealing the implanted dopant species to form the charge compensation region and so that the implant tails are not driven into the channel region.