Semiconductor device with self-aligned contact elements

Abstract

One method disclosed herein includes forming a sacrificial etch stop material in a recess above a replacement gate structure, with the sacrificial etch stop material in position, forming a self-aligned contact that is conductively coupled to the source/drain region, after forming the self-aligned contact, performing at least one process operation to expose and remove the sacrificial etch stop material in the recess so as to thereby re-expose the recess, and forming a third layer of insulating material in at least the re-exposed recess.

1 .- 20 . (canceled) 
     
     
         21 . A transistor device, comprising:
 a replacement gate structure positioned above a semiconductor substrate;   at least one sidewall spacer positioned adjacent said replacement gate structure;   a gate cap layer positioned above said replacement gate structure, said gate cap layer having an upper surface that is positioned a first distance above a surface of said substrate;   a first layer of insulating material formed above said substrate adjacent said sidewall spacer, said first layer of insulating material having an upper surface that is positioned a second distance above said surface of said substrate; and   a conductive contact positioned in an opening formed in at least said first layer of insulating material, said conductive contact being conductively coupled to a source/drain region of said transistor, said conductive contact having an upper surface that is positioned said second distance above said surface of said substrate, wherein said first distance is less than said second distance.   
     
     
         22 . The device of  claim 21 , further comprising an etch stop liner layer positioned between said at least one sidewall spacer and said first layer of insulating material. 
     
     
         23 . The device of  claim 21 , further comprising a VO contact positioned in a second layer of insulating material positioned above said first layer of insulating material and said gate cap layer, wherein said VO contact is conductively coupled to said conductive contact. 
     
     
         24 . A transistor device, comprising:
 a replacement gate structure positioned above a semiconductor substrate, said replacement gate structure having an upper surface;   at least one sidewall spacer positioned adjacent said replacement gate structure, said at least one sidewall spacer having an upper surface;   a first layer of insulating material formed above said substrate adjacent said at least one sidewall spacer, said first layer of insulating material having an upper surface, wherein, relative to an upper surface of said substrate, said upper surface of said replacement gate structure and said upper surface of said at least one sidewall spacer are positioned at a level below said upper surface of said first layer of insulating material, and wherein said first layer of insulating material, said upper surface of said replacement gate structure and said upper surfaces of said at least one sidewall spacer at least partially define a recessed gate cavity;   a conductive contact positioned in an opening formed in at least said first layer of insulating material, said conductive contact being conductively coupled to a source/drain region of said transistor; and   a second layer of insulating material positioned in at least said recessed gate cavity and above said first layer of insulating material.   
     
     
         25 . The device of  claim 24 , further comprising an etch stop liner layer positioned between said at least one sidewall spacer and said first layer of insulating material. 
     
     
         26 . The device of  claim 24 , wherein said conductive contact comprises an over-hang portion that is vertically positioned above at least a portion of said recessed gate cavity. 
     
     
         27 . The device of  claim 24 , wherein said second layer of insulating material is in contact with said upper surface of said replacement gate structure and said upper surface of said at least one sidewall spacer. 
     
     
         28 . A transistor device, comprising:
 a replacement gate structure positioned above a semiconductor substrate, said replacement gate structure having an upper surface;   at least one sidewall spacer positioned adjacent said replacement gate structure, said at least one sidewall spacer having an upper surface;   a first layer of insulating material formed above said substrate adjacent said sidewall spacer, said first layer of insulating material having an upper surface, wherein, relative to an upper surface of said substrate, said upper surface of said replacement gate structure and said upper surface of said sidewall spacer are positioned at a level below said upper surface of said first layer of insulating material, and wherein said first layer of insulating material, said upper surface of said replacement gate structure and said upper surface of said sidewall spacer at least partially define a recessed gate cavity;   an etch stop liner layer positioned between said at least one sidewall spacer and said first layer of insulating material;   a conductive contact positioned in an opening formed in at least said first layer of insulating material, said conductive contact being conductively coupled to a source/drain region of said transistor, wherein said conductive contact comprises an over-hang portion that is vertically positioned above at least a portion of said recessed gate cavity; and   a second layer of insulating material positioned in at least said recessed gate cavity and above said first layer of insulating material, wherein said second layer of insulating material is in contact with said upper surface of said replacement gate structure and said upper surface of said at least one sidewall spacer.   
     
     
         29 . A transistor device, comprising:
 a replacement gate structure positioned above a semiconductor substrate;   at least one sidewall spacer positioned adjacent said replacement gate structure;   a gate cap layer positioned above said replacement gate structure, said gate cap layer having an upper surface that is positioned a first distance above a surface of said substrate;   a first layer of insulating material formed above said substrate adjacent said sidewall spacer, said first layer of insulating material having an upper surface that is positioned a second distance above said surface of said substrate;   an etch stop liner layer positioned between said at least one sidewall spacer and said first layer of insulating material;   a conductive contact positioned in an opening formed in at least said first layer of insulating material, said conductive contact being conductively coupled to a source/drain region of said transistor, said conductive contact having an upper surface that is positioned said second distance above said surface of said substrate, wherein said first distance is less than said second distance; and   a VO contact positioned in a second layer of insulating material positioned above said first layer of insulating material and said gate cap layer, wherein said VO contact is conductively coupled to said conductive contact.