Vertical transistor, memory cell, device, system and method of forming same

Abstract

A memory device, system and fabrication method relating to a vertical memory cell including a semiconducting pillar extending outwardly from an integrally connected semiconductor substrate are disclosed. A first source/drain region is formed in the semiconductor substrate and a body region and a second source/drain region are formed within the semiconductor pillar. A first gate is coupled to a first side of the semiconductor pillar for coupling the first and second source/drain regions together when activated. The vertical memory cell also includes a storage capacitor formed on an extended end of the semiconducting pillar and electrically coupled to the second source/drain region.

1 . A method of using a semiconductor device, the method comprising:
 controlling conductive characteristics of an access transistor with a first signal applied to a first gate of the access transistor disposed on a first side of a pillar configured as a vertical transistor with a first source/drain region coupled to a bit line in a substrate, a body region over the first source/drain region, and a second source/drain region above the body region; and   modifying the conductive characteristics of the access transistor with a second signal applied to a second gate of the access transistor disposed on a second side of the pillar.   
     
     
         2 . The method of  claim 1 , wherein the first signal and the second signal are asynchronously asserted. 
     
     
         3 . The method of  claim 1 , wherein the first signal and the second signal are asynchronously negated. 
     
     
         4 . The method of  claim 1 , wherein the first signal and the second signal are synchronously applied. 
     
     
         5 . The method of  claim 4 , wherein the first signal and the second signal are applied with different activation voltages. 
     
     
         6 . The method of  claim 1 , wherein the first signal and the second signal are applied with different activation voltages. 
     
     
         7 . The method of  claim 1 , wherein the first signal and the second signal are applied with different activation voltages. 
     
     
         8 . A method of using a semiconductor device, the method comprising:
 applying a first signal to a first gate of a vertically oriented access transistor formed in a semiconductor pillar that extends outwardly from an underlying substrate; and   applying a second signal to a second gate of the vertically oriented transistor, the semiconductor pillar including a first source/drain region separated from a second source/drain region by a body region, and the first gate and the second gate being located on opposing sides of the semiconductor pillar.   
     
     
         9 . The method of  claim 8 , wherein applying the first signal to a first gate includes applying a positive potential to the first gate. 
     
     
         10 . The method of  claim 9 , wherein applying the second signal to a first gate includes applying a positive potential to the second gate. 
     
     
         11 . The method of  claim 10 , wherein applying the positive potential to the first gate and the positive potential to the second gate both occur at the same time. 
     
     
         12 . The method of  claim 8 , wherein applying a first signal to a first gate of a vertically oriented access transistor includes applying the first signal to a word line coupled to the first gate of the vertically oriented access transistor. 
     
     
         13 . The method of  claim 12 , wherein the wordline includes a pair of independently operable wordlines that independently apply the first signal to the first gate of the vertically oriented access transistor and another gate of a neighboring vertically oriented access transistor separated by an isolation trench. 
     
     
         14 . A method of using a semiconductor device, the method comprising:
 applying a first signal to at least one independently operable word line of a first word line pair disposed in a trench between a first row of vertically oriented access transistors and a second row of vertically oriented access transistors; and   applying a second signal to at least one independently operable word line of a second word line pair disposed in another trench between the first row of vertically oriented access transistors and a third row of vertically oriented access transistors, wherein each vertically oriented access transistor includes a first source/drain region and a second source/drain region separated by a body region in a semiconductor pillar extending outwardly from an underlying substrate.   
     
     
         15 . The method of  claim 14 , wherein applying the first signal to at least one independently operable word line of the first word line pair and applying the second signal to the at least one operably wordline of the second word line pair occur at a same time for a common vertically oriented access transistor. 
     
     
         16 . The method of  claim 14 , further comprising storing a charge in at least one storage capacitor disposed on the second source/drain region of its respective vertical oriented access transistor. 
     
     
         17 . The method of  claim 14 , further comprising addressing at least one memory cell in an array of memory cells with a combination of applying the first signal to the independently operably wordline of the first word line pair that is coupled to a first gate of a first vertically oriented access transistor, and applying the second signal to the independently operably wordline of the second word line pair that is coupled to a second gate of the first vertically oriented access transistor. 
     
     
         18 . The method of  17 , further comprising reading data from at least one storage capacitor disposed on the second source/drain region of its respective vertical oriented access transistor of the at least one memory cell. 
     
     
         19 . The method of  17 , further comprising writing data to at least one storage capacitor disposed on the second source/drain region of its respective vertical oriented access transistor of the at least one memory cell. 
     
     
         20 . The method of  claim 17 , applying a third signal to at least one bit line formed under at least a portion of a column of vertically oriented access transistors.