Circuits and methods for dfe with reduced area and power consumption

Abstract

A 1/n-rate decision feedback equalizer (DFE) and method include a plurality of branches. Each branch includes a summer circuit configured to add a feedback signal to a received input, and a latch configured to receive an output of the summer circuit in accordance with a clock signal. A feedback circuit includes a multiplexer configured to receive as input, an output of each branch, the multiplexer having a clocked select input and configured to multiplex the output of each branch to assemble a full rate bit sequence, and a filter configured to provide cancellation of intersymbol interference (ISI) from the received input to be provided to the summer circuit of each branch.

What is claimed is: 
     
         1 . A double regenerating latch, comprising:
 two cascaded differential regenerating latch stages to achieve improved speed and sensitivity; the stages including:
 a first stage having first input transistors of a first type, cross-coupled load transistors and reset transistors of a second type, and a second stage having second input transistors of the second type and cross-coupled load transistors of the first type, such that when the first stage is in an opaque state the reset transistors precharge outputs of the first stage to a power supply voltage, the second input transistors of the second stage are shut off to retain outputs at levels indicative of a previous stored bit, when the first stage is activated, the cross-coupled load transistors of the first stage and of the second type begin to regenerate an input signal and at a same time, an output common-mode of the first stage falls to turn on the second input transistors of the second stage, the second stage includes the cross-coupled load transistors of the first type and is switched after the output of the first stage achieves a threshold signal level to provide additional regenerative gain. 
   
     
     
         2 . The double regenerating latch as recited in  claim 1 , wherein the double regenerating latch receives an output from a slicer and the first stage enters regeneration while the slicer is still regenerating such that the first stage and the slicer regenerate simultaneously. 
     
     
         3 . The double regenerating latch as recited in  claim 2 , wherein the latch is employed in a decision feedback equalizer (DFE). 
     
     
         4 . The double regenerating latch as recited in  claim 3 , wherein the DFE includes a continuous-time infinite impulse response filter. 
     
     
         5 . The double regenerating latch as recited in  claim 3 , wherein previous stored bit is a decision bit. 
     
     
         6 . The double regenerating latch as recited in  claim 1 , wherein the first type includes NMOS and the second type includes PMOS. 
     
     
         7 . The double regenerating latch as recited in  claim 1 , wherein the first type includes PMOS and the second type includes NMOS.