Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a substrate, and a gate electrode formed on the substrate on a gate insulation film. The semiconductor device also includes a source diffusion layer and a drain diffusion layer which are formed on the substrate where the gate electrode is sandwiched between the source diffusion layer and the drain diffusion layer, one or more source contacts formed on the source diffusion layer; and one or more drain contacts formed on the drain diffusion layer. At least one of the source contacts and the drain contacts includes a first contact region having a first size and a second contact region having a second size larger than the first size on the same source diffusion layer or on the same drain diffusion layer.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;
 a gate electrode formed above the substrate; 
   a source diffusion layer and a drain diffusion layer which are formed within the substrate sandwiching the gate electrode therebetween;   one or more source contacts formed on the source diffusion layer; and   one or more drain contacts formed on the drain diffusion layer, wherein   at least one of the source contacts and drain contacts includes a first contact region having a first contact region having a first size and a second contact region having a second size greater than the first size on at least one of the same source diffusion layer and on the same drain diffusion layer.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein
 a resistance of the second contact region is 0.9 times to 1.1 times a resistance of N (N being an integer of 2 or more) first contact regions which are connected to each other in parallel.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein
 the semiconductor device is a 28 nm node generation or a node generation following the 28 nm node generation.   
     
     
         4 . The semiconductor device according to  claim 1 , wherein
 the first contact region and the second contact region are alternately arranged on the at least one of the source diffusion layer and the drain diffusion layer.   
     
     
         5 . The semiconductor device according to  claim 1 , wherein
 the first contact region formed on the source diffusion layer is arranged adjacent to the second contact region formed on the drain diffusion layer with the gate electrode sandwiched therebetween.   
     
     
         6 . The semiconductor device according to  claim 1 , wherein
 the second contact region formed on the source diffusion layer is arranged adjacent to the first contact formed on the drain diffusion layer with the gate electrode sandwiched therebetween.   
     
     
         7 . The semiconductor device according to  claim 1 , wherein
 the first contact region formed on the source diffusion layer is arranged adjacent to the second contact region formed on the drain diffusion layer with the gate electrode sandwiched therebetween, and   the second contact region formed on the source diffusion layer is arranged adjacent to the first contact formed on the drain diffusion layer with the gate electrode sandwiched therebetween.   
     
     
         8 . The semiconductor device according to  claim 1 , wherein
 a third contact region having a third size greater than the second size is formed on the at least one of the same source diffusion layer and on the same drain diffusion layer.   
     
     
         9 . The semiconductor device according to  claim 8 , wherein
 the first contact region formed on the source diffusion layer is arranged adjacent to the third contact region formed on the drain diffusion layer with the gate electrode sandwiched therebetween.   
     
     
         10 . The semiconductor device according to  claim 8 , wherein
 the first contact region formed on the drain diffusion layer is arranged adjacent to the third contact region formed on the source diffusion layer with the gate electrode sandwiched therebetween.   
     
     
         11 . The semiconductor device according to  claim 8 , wherein
 the first contact region, the second contact region and the third contact region are alternately arranged on the at least one of the source diffusion layer and the drain diffusion layer.   
     
     
         12 . A semiconductor device, comprising:
 a substrate;   a source diffusion layer and a drain diffusion layer provided on the substrate and spaced from one another   a gate electrode disposed on a gate insulation film disposed on the substrate, different portions of the gate electrode overlying the source region and the drain region;   one or more source contacts provided on the source diffusion layer; and   one or more drain contacts provided on the drain diffusion layer, wherein   at least one of the source contacts and the drain contacts includes a first contact having a first size and a second contact having a second size greater than the first size located on at least one of a single source diffusion layer and a single drain diffusion layer.   
     
     
         13 . The semiconductor device according to  claim 12 , wherein
 the resistance of the second contact region is 0.9 times to 1.1 times the resistance of N (N being an integer of 2 or more) first contact regions connected to each other in parallel.   
     
     
         14 . The semiconductor device according to  claim 12 , wherein
 the semiconductor device is a 28 nm node generation or a node generation following the 28 nm node generation.   
     
     
         15 . The semiconductor device according to  claim 12 , wherein
 the first contact and the second contact are alternately arranged on at least one of the single source diffusion layer and the single drain diffusion layer.   
     
     
         16 . The semiconductor device according to  claim 12 , wherein
 the first contact disposed on the source diffusion layer is adjacent to the second contact disposed on the drain diffusion layer.   
     
     
         17 . A semiconductor device, comprising:
 a substrate;   a gate electrode disposed on a gate insulation film disposed on the substrate;   a source diffusion layer and a drain diffusion layer provided on the substrate the gate electrode extending therebetween;   source plurality of contacts provided on at least one of the source diffusion layer and the drain diffusion layer, wherein   at least one of the one or more contacts disposed on at least one of the source and the drain regions include at least two contacts having different areas of contact with the source or drain region.   
     
     
         18 . The semiconductor device according to  claim 17 , wherein
 the at least two contacts comprise a length and a width in contact with the source or drain region;   the contacts have the same length and different widths; and   the gate electrode is spaced the two contacts in the source or drain regions and extends in the width direction.   
     
     
         19 . The semiconductor device according to  claim 17 , wherein
 the at least two contacts comprise a length and a width in contact with the source or drain region;   the contacts have the same length and different widths; and   the gate electrode is spaced the two contacts in the source or drain regions and extends in the length direction.   
     
     
         20 . The semiconductor device according to  claim 17 , further including:
 a third contact region having a third area in contact with the source or drain region with which the first and second contacts contact, the third area greater than the contact area of both the first and the second contacts with the source or drain region.