Component, for example nmos transistor, with active region with relaxed compression stresses, and fabrication method

Abstract

An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by a trench insulating region. The transistor, active region and trench insulating region are covered by an additional insulating region. A metal contact extends through the additional insulating region to make contact with the trench insulating region. The metal contact may penetrate into the trench insulating region.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a substrate including an active region delimited by a trench insulating region;   a component unfavorably sensitive to stress arranged at least partially in the active region;   an additional insulating region arranged over the component, the active region and the trench insulating region; and   a contact region passing through said additional insulating region and contacting at least a top surface face of a portion of said trench insulating region;   wherein said contact region is formed by at least one material different from a material forming said trench insulating region and said additional insulating region.   
     
     
         2 . The integrated circuit according to  claim 1 , wherein said at least one material of the contact region comprises a metal. 
     
     
         3 . The integrated circuit according to  claim 2 , wherein the component is a transistor and wherein said metal is a same metal as used for making electrical contact to said transistor. 
     
     
         4 . The integrated circuit according to  claim 1 , wherein the contact region penetrates into said portion of said trench insulating region to a depth below an upper surface of the substrate. 
     
     
         5 . The integrated circuit according to  claim 1 , wherein said additional insulating region comprises an etch stop layer in compressed stress, said contact region penetrating through said etch stop layer. 
     
     
         6 . The integrated circuit according to  claim 1 , wherein said additional insulating region comprises an etch stop layer in tensile stress, said contact region penetrating through said etch stop layer. 
     
     
         7 . The integrated circuit according to  claim 6 , wherein said contact region is also in tensile stress. 
     
     
         8 . The integrated circuit according to  claim 1 , wherein said additional insulating region comprises an etch stop layer, and further comprising at least one protuberance arranged over at least a part of said trench insulating region and below said etch stop layer. 
     
     
         9 . The integrated circuit according to  claim 8 , wherein said etch stop layer is in compressed stress. 
     
     
         10 . The integrated circuit according to  claim 8 , wherein said component is a transistor having a transistor gate including a gate electrode and sidewall spacers. 
     
     
         11 . The integrated circuit according to  claim 10 , wherein said protuberance has a structure similar to that of the transistor gate including an electrode and sidewall spacers. 
     
     
         12 . The integrated circuit according to  claim 11 , wherein the gate electrode of the transistor gate extends over the trench insulating region and is spaced from said protuberance. 
     
     
         13 . The integrated circuit according to  claim 1 , further comprising:
 an additional active region delimited by the trench insulating region;   an additional component unfavorably sensitive to compression stresses arranged at least partially in the additional active region;   wherein said trench insulating region comprises at least one area adjacent the second active region formed by two insulating extents that are mutually separated by a separation region formed by a part of the substrate.   
     
     
         14 . The integrated circuit according to  claim 13 , wherein said separation region has a top face situated substantially at a same level as an upper surface of the additional active region. 
     
     
         15 . The integrated circuit according to  claim 13 , wherein the insulating extent situated closest to said additional active region has a cross-sectional area less than or equal to a cross-sectional area of the insulating extent situated further away from the additional active region. 
     
     
         16 . The integrated circuit according  claim 13 , wherein said separation region at least partially surrounds said additional active region. 
     
     
         17 . The integrated circuit according to  claim 13 , wherein said contact region is positioned between the active area and the additional active area. 
     
     
         18 . The integrated circuit according to  claim 13 , further comprising:
 an additional contact region passing through said additional insulating region and contacting at least a top surface face of a portion of said trench insulating region;   wherein said additional contact region is formed by at least one material different from the material forming said trench insulating region and said additional insulating region.   
     
     
         19 . The integrated circuit according to  claim 18 , wherein said at least one material of the contact region and additional contact region comprises a metal. 
     
     
         20 . The integrated circuit according to  claim 18 , wherein the additional contact region contacts the insulating extent situated closest to said additional active region. 
     
     
         21 . The integrated circuit according to  claim 18 , wherein the additional contact region penetrates into the insulating extent situated closest to said additional active region to a depth below an upper surface of the substrate. 
     
     
         22 . The integrated circuit according to  claim 18 , wherein said additional insulating region comprises an etch stop layer in compressed stress, said additional contact region penetrating through said etch stop layer. 
     
     
         23 . The integrated circuit according to  claim 18 , wherein said additional insulating region comprises an etch stop layer in tensile stress, said additional contact region penetrating through said etch stop layer. 
     
     
         24 . The integrated circuit according to  claim 23 , wherein said additional contact region is also in tensile stress. 
     
     
         25 . A method relaxing of stress in an active region of a substrate supporting a component unfavorably sensitive to stress, comprising:
 forming a trench insulating region around the active region;   forming an additional insulating region arranged over the component, the active region and the insulating region;   forming a contact region passing through said additional insulating region to reach said trench insulating region;   wherein the contact region is formed by at least one material different from materials forming said insulating region and said additional insulating region.   
     
     
         26 . The method according to  claim 25 , wherein the contact region penetrates into said insulating region. 
     
     
         27 . The method according to  claim 25 , wherein said additional insulating region comprises an etch stop layer in compressed stress, said contact region penetrating through said etch stop layer. 
     
     
         28 . The method according to  claim 25 , wherein said additional insulating region comprises an etch stop layer in tensile stress, said contact region penetrating through said etch stop layer. 
     
     
         29 . The method according to  claim 28 , wherein said contact region is also in tensile stress. 
     
     
         30 . The method according to  claim 25 , further comprising:
 forming at least one protuberance arranged over at least a part of said trench insulating region and under a compressed bottom insulating layer of said additional insulating region.   
     
     
         31 . The method according to  claim 30 , wherein said component is a transistor having a transistor gate including a gate electrode and sidewall spacers, and wherein said protuberance has a structure similar to that of the transistor gate including an electrode and sidewall spacers.