Semiconductor device

Abstract

According to one embodiment, a first transistor includes a first semiconductor region, a second semiconductor region, a third semiconductor region, a first gate insulating film, and a first gate electrode. The first semiconductor region is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line. The second semiconductor region is provided above the first semiconductor region in the first semiconductor layer. The third semiconductor region is provided above the second semiconductor region in the first semiconductor layer. The first gate insulating film covers a first side face of the first semiconductor layer. The first gate electrode covers the first side face of the first semiconductor layer through the first gate insulating film. The first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first line configured to extend in a first direction along a surface of a semiconductor substrate; and   a first transistor configured to be disposed above the first line,   wherein the first transistor includes   a first semiconductor region which is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line,   a second semiconductor region which is provided above the first semiconductor region in the first semiconductor layer,   a third semiconductor region which is provided above the second semiconductor region in the first semiconductor layer,   a first gate insulating film which covers a first side face of the first semiconductor layer, and   a first gate electrode which covers the first side face of the first semiconductor layer through the first gate insulating film, and   wherein the first transistor has an asymmetrical structure with respect to a center face of the second semiconductor region in the second direction.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein
 an overlap length between the first gate electrode and the first semiconductor region in the second direction is different from an overlap length between the first gate electrode and the third semiconductor region in the second direction.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein
 an impurity concentration of the first semiconductor region is different from an impurity concentration of the third semiconductor region.   
     
     
         4 . The semiconductor device according to  claim 1 , wherein
 a shape of the first gate electrode is asymmetrical with respect to the center face.   
     
     
         5 . The semiconductor device according to  claim 1 , further comprising:
 a second semiconductor layer configured to be connected to an upper face of the first semiconductor layer and to extend in the second direction;   a plurality of second lines configured to extend in a third direction along the surface of the semiconductor substrate and to intersect with the second semiconductor layer above the first transistor; and   a plurality of memory cells configured to be disposed at positions where the second semiconductor layer and the plurality of second lines intersect.   
     
     
         6 . The semiconductor device according to  claim 5 , wherein
 each of the plurality of memory cells is reset from a low resistance state to a high resistance state by making voltage of the first line higher than voltage of the second line, and   an overlap length between the first gate electrode and the first semiconductor region in the second direction is smaller than an overlap length between the first gate electrode and the third semiconductor region in the second direction.   
     
     
         7 . The semiconductor device according to  claim 5 , wherein
 each of the plurality of memory cells is reset from a low resistance state to a high resistance state by making voltage of the second line higher than voltage of the first line, and   an overlap length between the first gate electrode and the third semiconductor region in the second direction is smaller than an overlap length between the first gate electrode and the first semiconductor region in the second direction.   
     
     
         8 . The semiconductor device according to  claim 5 , wherein
 each of the plurality of memory cells is reset from a low resistance state to a high resistance state by making voltage of the first line higher than voltage of the second line, and   an impurity concentration of the first semiconductor region is lower than an impurity concentration of the third semiconductor region.   
     
     
         9 . The semiconductor device according to  claim 5 , wherein
 each of the plurality of memory cells is reset from a low resistance state to a high resistance state by making voltage of the second line higher than voltage of the first line, and   an impurity concentration of the third semiconductor region is lower than an impurity concentration of the first semiconductor region.   
     
     
         10 . The semiconductor device according to  claim 5 , wherein
 each of the plurality of memory cells is reset from a low resistance state to a high resistance state by making voltage of the first line higher than voltage of the second line, and   a face of the first gate electrode which abuts on the first gate insulating film is curved so that a lower portion thereof is spaced apart from the first semiconductor layer.   
     
     
         11 . The semiconductor device according to  claim 10 , wherein
 a film thickness of the first gate insulating film on an upper side portion in the first direction is thicker than a film thickness on a lower side portion in the second direction.   
     
     
         12 . The semiconductor device according to  claim 5 , wherein
 each of the plurality of memory cells is reset from a low resistance state to a high resistance state by making voltage of the second line higher than voltage of the first line, and   a face of the first gate electrode which abuts on the first gate insulating film is curved so that an upper portion is spaced apart from the first semiconductor layer.   
     
     
         13 . The semiconductor device according to  claim 12 , wherein
 a film thickness of the first gate insulating film on an upper side portion in the first direction is thicker than a film thickness on a lower side portion in the second direction.   
     
     
         14 . A semiconductor device comprising:
 a first line configured to extend in a first direction along a surface of a semiconductor substrate; and   a first transistor configured to be disposed above the first line,   wherein the first transistor includes   a first semiconductor region which is provided in a first semiconductor layer extending in a second direction substantially perpendicular to the surface of the semiconductor substrate from the first line,   a second semiconductor region which is provided above the first semiconductor region in the first semiconductor layer,   a third semiconductor region which is provided above the second semiconductor region in the first semiconductor layer,   a first gate insulating film which covers a first side face of the first semiconductor layer, and   a first gate electrode which covers the first side face of the first semiconductor layer through the first gate insulating film, and   wherein a face of the first gate electrode which abuts on the first gate insulating film is curved so that an upper portion of the first gate electrode in the second direction is spaced apart from the first semiconductor layer.   
     
     
         15 . The semiconductor device according to  claim 14 , wherein
 a curvature of a lower end of the first gate electrode is larger than a curvature of an upper end of the first gate electrode.   
     
     
         16 . The semiconductor device according to  claim 15 , further comprising:
 a second semiconductor layer configured to be connected to an upper face of the first semiconductor layer and to extend in the second direction;   a plurality of second lines configured to extend in a third direction along the surface of the semiconductor substrate and to intersect with the second semiconductor layer above the first transistor; and   a plurality of memory cells configured to be disposed at positions where the second semiconductor layer and the plurality of second lines intersect.