Split-gate flash memory exhibiting reduced interference

Abstract

A split gate memory cell is fabricated with a dielectric spacer comprising a high-k material between the word gate and the memory gate stack. Embodiments include memory cells with a dielectric spacer comprising low-k and high-k layers. Other embodiments include memory cells with an air gap between the word gate and the memory gate stack.

What is claimed is: 
     
         1 . A device comprising:
 a memory gate stack over a substrate;   a word gate over the substrate; and   a first dielectric spacer between the word gate and the memory gate stack, the dielectric spacer comprising a low-k layer and a first high-k layer, each layer being formed on the substrate to a same height over the entire length of the low-k and first high-k layers, the dielectric spacer occupying the entire space between the memory gate stack and the word gate.   
     
     
         2 . The device according to  claim 1 , wherein the first high-k layer is proximate a first side surface of the memory gate stack. 
     
     
         3 . The device according to  claim 2 , comprising a work function tuning layer between the memory gate stack and the first high-k layer. 
     
     
         4 . The device according to  claim 2 , wherein the first dielectric spacer comprises a second high-k layer proximate the word gate. 
     
     
         5 . The device according to  claim 4 , comprising a work function tuning layer between the memory gate stack and the first high-k layer and/or between the word gate and the second high-k layer. 
     
     
         6 . The device according to  claim 2 , comprising a second dielectric spacer comprising a high-k layer proximate the second side surface of the memory gate stack and a low-k layer. 
     
     
         7 . A device comprising a memory gate stack over a substrate; a word gate over the substrate; and a first air gap between the word gate and a first side surface of the memory gate stack. 
     
     
         8 . The device according to  claim 7 , comprising a second air gap proximate a second side surface of the memory gate stack. 
     
     
         9 . The device according to  claim 1 , wherein the dielectric spacer is on opposite side surfaces of the memory gate stack. 
     
     
         10 . The device according to  claim 9 , wherein the dielectric spacer comprises the first high-k layer proximate the opposite side surfaces of the memory gate stack and the low-k layer. 
     
     
         11 . The device according to  claim 10 , wherein the dielectric spacer comprises a second high-k layer proximate the word gate. 
     
     
         12 . A device comprising:
 a memory gate stack on a substrate;   a word gate on the substrate; and   a first dielectric spacer between the word gate and the memory gate stack, the dielectric spacer comprising two layers, each layer being formed on the substrate to a same height over the entire length of the two layers, the dielectric spacer occupying the entire space between the memory gate stack and the word gate.   
     
     
         13 . The device according to  claim 12 , wherein a first one of the two layers is proximate a first side surface of the memory gate stack. 
     
     
         14 . The device according to  claim 13 , comprising a work function tuning layer between the memory gate stack and the first one of the two layers. 
     
     
         15 . The device according to  claim 13 , wherein the first dielectric spacer comprises a second one of the two layers proximate the word gate. 
     
     
         16 . The device according to  claim 15 , comprising a work function tuning layer between the memory gate stack and the first one of the two layers and/or between the word gate and the second one of the two layers. 
     
     
         17 . The device according to  claim 13 , comprising a second dielectric spacer comprising a high-k layer proximate the second side surface of the memory gate stack and a low-k layer. 
     
     
         18 . The device according to  claim 12 , wherein the dielectric spacer comprises a first high-k layer proximate the opposite side surfaces of the memory gate stack and the low-k layer. 
     
     
         19 . The device according to  claim 18 , wherein the dielectric spacer comprises a second high-k layer proximate the word gate.