Semiconductor device and system using the same

Abstract

There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set to an OFF state.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a pair of terminals;   a normally-off first transistor provided with a gate, a source, and a drain; and   a normally-on second transistor which is a SiC compound transistor provided with a gate, a source, and a drain, of which a source-to-drain path is coupled between the pair of terminals via a source-to-drain path of the first transistor,   wherein the gate of the first transistor and the gate of the second transistor are both driven to have a period in which the second transistor is set to an off state before the first transistor.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the first transistor is a MOSFET. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein, the gate of the first transistor and the gate of the second transistor are both driven to have another period in which the first transistor is set to an on state before the second transistor. 
     
     
         4 . The semiconductor device according to  claim 3 ,
 wherein the second transistor and the first transistor are sealed in one package,   wherein the gate of the first transistor is coupled to a first lead projected from the package,   wherein the source of the first transistor is coupled to a second lead projected from the package,   wherein the gate of the second transistor is coupled to a third lead projected from the package, and   wherein the drain of the second transistor is coupled to a fourth lead projected from the package.   
     
     
         5 . The semiconductor device according to  claim 1 , further comprising:
 a delay circuit which receives one input signal to drive both the first transistor and the second transistor, and has a plurality of first inverters to delay the one input signal to drive the first transistor when setting the first transistor and the second transistor to the off state.   
     
     
         6 . The semiconductor device according to  claim 1 , wherein the delay circuit further has a plurality of second inverters to delay the one input signal to drive the second transistor when setting the first transistor and the second transistor to an on state. 
     
     
         7 . A system comprising:
 a load device; and   a first semiconductor device and a second semiconductor device each coupled to the load device,   wherein each of the first semiconductor device and the second semiconductor device comprise:
 a pair of terminals, 
 a normally-off first transistor provided with a gate, a source, and a drain, 
 a normally-on second transistor which is a SiC compound transistor provided with a gate, a source, and a drain, of which a source-to-drain path is coupled between the pair of terminals via a source-to-drain path of the first transistor, 
 wherein the gate of the first transistor and the gate of the second transistor are both driven to have a period in which the second transistor is set to an off state before the first transistor, and 
   wherein one of the pair of terminals in the first semiconductor device is coupled to the load device, and one of the pair of terminals in the second semiconductor device is coupled to the load device.   
     
     
         8 . The system according to  claim 7 , wherein each of the first semiconductor device and the second semiconductor device further comprise:
 a delay circuit which receives one input signal to drive both the first transistor and the second transistor, and has a plurality of first inverters to delay the one input signal to the first transistor when setting the first transistor and the second transistor to the off state.   
     
     
         9 . The system according to  claim 8 , wherein the delay circuit further has a plurality of second inverters to delay the one input signal to the second transistor when setting the first transistor and the second transistor to an on state. 
     
     
         10 . The system according to  claim 9 , wherein the first transistor is set to the on state before the second transistor. 
     
     
         11 . The system according to  claim 7 , wherein in each of the first semiconductor device and the second semiconductor device, the first transistor is a MOSFET. 
     
     
         12 . The system according to  claim 7 , wherein, when one of the first transistor and the second transistor in the first semiconductor device is set to an on state, the first transistor and the second transistor in the second semiconductor device are set to the off state. 
     
     
         13 . The system according to  claim 12 ,
 wherein the load device includes a motor.   
     
     
         14 . The system according to  claim 12 ,
 wherein the load device includes a coil.   
     
     
         15 . A system comprising:
 a load device;   an inverter circuit coupled to the load device, and which comprises:
 a pair of terminals, 
 a normally-off first transistor provided with a gate, a source, and a drain, and 
 a normally-on second transistor which is a SiC compound transistor provided with a gate, a source, and a drain, of which a source-to-drain path is coupled between the pair of terminals via a source-to-drain path of the first transistor; 
   a control circuit to drive the inverter circuit, and, in response to an input signal, the control circuit supplies a first control signal to the gate of the first transistor and a second control signal to the gate of the second transistor, so the first transistor and the second transistor have a period in which the second transistor is set to an off state before the first transistor; and   a delay circuit which receives the one input signal, and has a plurality of first inverters to delay the first control signal to the first transistor when setting the first transistor and the second transistor to the off state.   
     
     
         16 . The semiconductor device according to  claim 15 , wherein the delay circuit has a plurality of second inverters to delay the second control signal to the second transistor when setting the first transistor and the second transistor to an on state. 
     
     
         17 . The semiconductor device according to  claim 15 , wherein the first transistor is a MOSFET. 
     
     
         18 . The semiconductor device according to  claim 15 , wherein, when setting the first transistor and the second transistor to an on state, the first transistor is set to the on state before the second transistor. 
     
     
         19 . The semiconductor device according to  claim 18 , wherein, when the first transistor and the second transistor are set to the on state, the pair of terminals are set to a conductive state. 
     
     
         20 . The semiconductor device according to  claim 15 , wherein, when the first transistor and the second transistor are set to the off state, the pair of terminals are set to a non-conductive state.