Enhancement of iso-via reliability

Abstract

A semiconductor structure and a process for forming a semiconductor structure. There is a back end of the line wiring layer which includes a wiring line and an ILD layer. A metal-filled via extends through the ILD layer to make contact with the wiring line. There is a reliability enhancement material that surrounds at least part of the via so as to render the via compressive where the via contacts the wiring line. The reliability enhancement material may be compressive as deposited or may be made compressive after deposition.

What is claimed is: 
     
         1 . A semiconductor structure comprising:
 a semiconductor base comprising a plurality of semiconductor devices:   a back end of the line wiring layer comprising:
 a wiring line; 
 an interlayer dielectric (ILD) layer on the wiring line; 
 a via extending through the ILD to communicate with the wiring line; 
 a metal filling the via and in contact with the wiring line; and 
 a compressive reliability enhancement material surrounding at least part of the metal-filled via to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress. 
   
     
     
         2 . The semiconductor structure of  claim 1  wherein the reliability enhancement material surrounds the entire metal-filled via. 
     
     
         3 . The semiconductor structure of  claim 1  wherein the reliability enhancement material surrounds the metal-filled via in the cap and only in a portion of the ILD. 
     
     
         4 . The semiconductor structure of  claim 1  further comprising a cap layer between the wiring line and the ILD layer and wherein the reliability enhancement material surrounds the metal-filled via only in the cap layer. 
     
     
         5 . The semiconductor structure of  claim 1  wherein the reliability enhancement material surrounds the metal-filled via only in a portion of the ILD. 
     
     
         6 . The semiconductor structure of  claim 1  wherein the reliability enhancement material surrounds the metal-filled via only where the metal-filled via contacts the wiring line. 
     
     
         7 . The semiconductor structure of  claim 1  wherein the via has a via wall and further comprising a barrier layer on the via wall between the via wall and the metal filling the via. 
     
     
         8 . The semiconductor structure of  claim 1  wherein the reliability enhancement material is selected from the group of materials consisting of silicon nitride, silicon carbide and silicon carbide nitride. 
     
     
         9 . The semiconductor structure of  claim 1  further comprising a cap layer between the wiring line and the ILD layer and wherein the reliability enhancement material is selected from the group of materials consisting of silicon nitride, silicon carbide and silicon carbide nitride. 
     
     
         10 . The semiconductor structure of  claim 9  wherein the cap layer is selected from the group consisting of silicon nitride and silicon carbide plus nitrogen. 
     
     
         11 . The semiconductor structure of  claim 9  wherein the reliability enhancement material is separate from the cap layer. 
     
     
         12 . A semiconductor structure comprising:
 a semiconductor base comprising a plurality of semiconductor devices:   a back end of the line wiring layer comprising:
 a wiring line; 
 an interlayer dielectric (ILD) layer on the wiring line; 
 a via extending through the ILD to communicate with the wiring line, wherein the via has a via wall; 
 a barrier layer on the via wall; 
 a metal filling the via in contact with the barrier layer and in contact with the wiring line; and 
 a compressive reliability enhancement material surrounding at least part of the metal-filled via to make a bottom of the metal-filled via that contacts the wiring line be under compressive stress. 
   
     
     
         13 . The semiconductor structure of  claim 12  wherein the reliability enhancement material surrounds the entire metal-filled via. 
     
     
         14 . The semiconductor structure of  claim 12  wherein the reliability enhancement material surrounds the metal-filled via in the cap and only in a portion of the ILD. 
     
     
         15 . The semiconductor structure of  claim 12  further comprising a cap layer between the wiring line and the ILD layer and wherein the reliability enhancement material surrounds the metal-filled via only in the cap layer. 
     
     
         16 . The semiconductor structure of  claim 12  wherein the reliability enhancement material surrounds the metal-filled via only in a portion of the ILD. 
     
     
         17 . The semiconductor structure of  claim 12  wherein the reliability enhancement material surrounds the metal-filled via only where the metal-filled via contacts the wiring line. 
     
     
         18 . A process of making a semiconductor structure comprising:
 forming a wiring line;   forming a recess in the wiring line;   filling the recess with a reliability enhancement material;   forming a cap layer over the wiring line and the recess;   forming an interlayer dielectric (ILD) layer on the cap layer;   forming a via opening through the ILD layer, cap layer and reliability enhancement material to expose a surface of the wiring line; and   filling the via opening with a metal to form a metal-filled via in contact with the wiring line;   wherein the reliability enhancement material causes a compressive stress on the metal-filled via where it contacts the wiring line.   
     
     
         19 . The process of  claim 18  wherein the reliability enhancement material is deposited so as to be compressive. 
     
     
         20 . The process of  claim 18  further comprising after forming a reliability enhancement material, treating the reliability enhancement material so as to be compressive.