US2015254820A1PendingUtilityA1

Semiconductor integrated circuit and multi-angle video system

Assignee: RENESAS ELECTRONICS CORPPriority: Oct 27, 2010Filed: May 21, 2015Published: Sep 10, 2015
Est. expiryOct 27, 2030(~4.2 yrs left)· nominal 20-yr term from priority
H04N 23/90H04N 23/698H04N 25/61H04N 5/77G06T 2200/28H04N 5/2173G06T 5/006H04N 5/357G06T 2207/10004H04N 5/907G06T 5/80
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Claims

Abstract

The present invention is provided to lessen load on a bus in the case of storing image data captured by a plurality of cameras into a semiconductor memory. To a semiconductor integrated circuit, a plurality of cameras and a semiconductor memory can be coupled. The semiconductor integrated circuit includes a plurality of first interfaces, a second interface, a bus, and a plurality of image processing modules. The image processing modules include a process of performing distortion correction on image data in a pre-designated region, and writing the image data in the region subjected to the distortion correction into the semiconductor memory via the bus and the second interface. By excluding image data out of the pre-designated region from an object of distortion correction in the image processing modules, the amount of image data transferred to the semiconductor memory is reduced.

Claims

exact text as granted — not AI-modified
1 - 7 . (canceled) 
     
     
         8 . A semiconductor integrated circuit on a single semiconductor substrate and for use with a camera and a semiconductor memory, comprising:
 a first interface configured to fetch first image data captured by the camera;   an image processing module coupled to the first interface and configured to perform a predetermined data process on the first image data received from the first interface and configured to output corrected image data, the predetermined data process comprising
 a process of extracting second image data from a pre-designated region of the first image data fetched by the first interface; 
 a process of performing distortion correction on the extracted second image data to provide the corrected image data; and 
 a process of writing the corrected image data into the semiconductor memory; 
   a bus coupled to outputs of the image processing module; and   a second interface coupled to the bus and configured to transmit the corrected image data to the semiconductor memory and to receive the corrected image data from the semiconductor memory.   
     
     
         9 . The semiconductor integrated circuit according to  claim 8 , further comprising:
 a display control unit configured to fetch the corrected image data stored in the semiconductor memory, synthesize the corrected image data, and display the resultant image data on a display device.   
     
     
         10 . The semiconductor integrated circuit according to  claim 9 ,
 wherein the image processing module includes:
 a line memory configured to store the first image data received via the first interface; 
 a display list buffer configured to store a display list; and 
 a process circuit configured to perform the distortion correction on the first image data in the line memory in accordance with the display list. 
   
     
     
         11 . The semiconductor integrated circuit according to  claim 10 ,
 wherein the display list includes:
 a first command for instructing coordinate transformation of image data stored in the line memory and storage of the coordinate-transformed image data into the semiconductor memory; 
 a second command for making execution of a next display list waited until a predetermined condition is satisfied; and 
 a third command for generating a predetermined interruption signal at a timing point when image data of one screen is obtained by process in the process circuit, and the process circuit executes the first, second, and third commands. 
   
     
     
         12 . The semiconductor integrated circuit according to  claim 11 , further comprising:
 a central processing unit coupled to the bus,   wherein the central processing unit is configured to write corresponding image data in the semiconductor memory into the display control unit via the bus by an interrupting process corresponding to an interruption signal caused by the third command in the display list.   
     
     
         13 . The semiconductor integrated circuit according to  claim 12 , further comprising:
 a port which outputs a sync signal for controlling the image capturing timings of the camera.

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